Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

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Tigerick

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As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.



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Intel Core Ultra 100 - Meteor Lake

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As mentioned by Tomshardware, TSMC will manufacture the I/O, SoC, and GPU tiles. That means Intel will manufacture only the CPU and Foveros tiles. (Notably, Intel calls the I/O tile an 'I/O Expander,' hence the IOE moniker.)



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Josh128

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IIRC Kepler said ~7700X perf so doubt Zen 6C can achieve that with its lower clocks (N3P not N2 like desktop).
Maybe Sony will use custom solution with a shared L2 between CPU and GPU.

PS6 GPU is very weak, based on old game testing as weak or weaker than a Ryzen 1700. Coding to the metal + offloading IO to dedicated logic really pays off.
7700X CPU? Zen 6C will probably be able to achieve that with ~4 to ~4.5 GHz, which shouldnt be a problem on N2.

PS6 GPU vs Ryzen 1700CPU?? Are you conflating CPUs and GPUs?
 

DavidC1

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View attachment 129034

edit
Test uses B580
Somehow I am not excited should have used 9070XT or 4080
B580 exacerbates the differences between the CPUs because Intel neglected driver optimization on their HD Audi.... I mean HD Graphics. It's at 100+ fps too, meaning it cares more about CPU differences. C&C is the best we got, but this is why I say the modern best is a shadow of the former best such as ixbtlabs, Anandtech, Xbitlabs. Actually, TPU is ok, but they don't go over everything.

From C&C
Skymont isn’t where Pentium M was in that era, nor does Intel’s Lion Cove P-Core suffer the inefficiencies Netburst did.
Lulz. Lion Cove is plenty inefficient. Of course it's not Netburst inefficient, but it's 2025's Netburst. If it was Netburst inefficient, Intel would have zero sales on their desktop parts, and Arrowlake would have underperformed Skylake per clock and used 500W. What do they say? "History doesn't repeat, but rhymes?" And the E core team that made Skymont is going to replace the P core team and design too. I find C&C's Lion Cove fanboyism funny.

Oh, and it's at different clock speeds too.
 
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Magras00

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Couldn't reply directly to #21,202, for some reason spam filter keeps flagging the username.

PS6 uses N3P so this could impact frequencies and matching 7700X with higher memory latencies, -1ghz to boost clocks and less L3 sounds very unlikely. Maybe the Kepler_L2 estimate factors in FF HW offloading (IO logic) otherwise there's no way Zen 6C gets 20-25% higher IPC than Zen 5 desktop. If we're talking 16-32MB full 8 x Zen 6 core config then the figure makes sense.

No I meant CPU. Post was a mess but I've fixed it now.
 
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511

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I think 3000+ ST and 14K-15K multi for the 4+8+4 variant would be better at 30-35W.
As for stagnation I doubt we will get ST Improvements just cause the fact that CGC is LNC+ so expect ~3-5% at best from cores and clock speeds I doubt they can do 5.7 GHz on mobile H series likely to be stuck at 5.4 GHz so expect 5-8% ST improvement.
Just for reference 285H does ~2900 ST so 3000-3100 would be good enough.

 
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Magio

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I think 3300 would be underwhelming considering the ARM side will do 4000 at better efficiency and Zen6 also most likely will be 3500+, but sadly I think ST will just be underwhelming and 3300 would be fine as damage limitation.

I agree with @511 that 3000+/14+k at OK efficiency would already be nice.
 

511

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Magio

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That's true and that's why I'm not saying PTL should outright match them but you'd still want it to keep up a bit better than this or start to at least match them in efficiency.

But that's of course not a realistic outcome for PTL and the minor improvements expected on Cougar Cove. Even further P core improvement seem unlikely to do that, and an unified core is still way too far away to make predictions.
 
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Covfefe

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Jul 23, 2025
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B580 exacerbates the differences between the CPUs because Intel neglected driver optimization on their HD Audi.... I mean HD Graphics. It's at 100+ fps too, meaning it cares more about CPU differences. C&C is the best we got, but this is why I say the modern best is a shadow of the former best such as ixbtlabs, Anandtech, Xbitlabs. Actually, TPU is ok, but they don't go over everything.

From C&C

Lulz. Lion Cove is plenty inefficient. Of course it's not Netburst inefficient, but it's 2025's Netburst. If it was Netburst inefficient, Intel would have zero sales on their desktop parts, and Arrowlake would have underperformed Skylake per clock and used 500W. What do they say? "History doesn't repeat, but rhymes?" And the E core team that made Skymont is going to replace the P core team and design too. I find C&C's Lion Cove fanboyism funny.

Oh, and it's at different clock speeds too.

Yeah, they did the same thing in their last skymont article.

The overall performance picture though, is that Skymont is still not at the same level as a high performance core. It’s behind in SPEC CPU2017’s integer suite, which represents a favorable set of workloads for a wide core with relatively weak vector execution. In vector-heavy workloads, it’s still hit or miss against Zen 2. Thus Skymont lacks the performance to replace Lion Cove or take on AMD’s best.


I found that Zen2 comparison particularly odd. They focused on the one area where Skymont is most deficient, and will see huge improvements in the next couple years (FP/SIMD). An alternative universe Skymont with a dense 4x512bit FPU could still be under 2mm^2.
 

DavidC1

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So by what Metric we would consider Panther Lake a Success?
Expected few % faster ST improvements, the MT performance expected out of a 4+8 and Lunarlake level battery life would be considered a success, since if we believe Intel, it should be cheaper.
I think 3300 would be underwhelming considering the ARM side will do 4000 at better efficiency and Zen6 also most likely will be 3500+, but sadly I think ST will just be underwhelming and 3300 would be fine as damage limitation.
You can't expect big performance gains from Pantherlake. Best is Lunarlake efficiency but with 4+8 instead of 4+4.
I found that Zen2 comparison particularly odd. They focused on the one area where Skymont is most deficient, and will see huge improvements in the next couple years (FP/SIMD). An alternative universe Skymont with a dense 4x512bit FPU could still be under 2mm^2.
It isn't even that deficient. Making an efficient use of xtors requires some sacrifices, meaning it'll be slow in some corner case scenarios. You won't make much progress in the next few years by not carefully considering efficiency in every part of design with Moore's Law gains crashing.

Even with AMD having full AVX-512 units, you can see most of the gains are from the instruction set, not the 512-bit vectors. Of course 512-bit is faster, but there's a point where it makes no sense anymore. You could go 1024, 2048, 4096 and on and on. At one point you have to stop. Yes you'll upset some people but you can't please everyone. They should stick to double pumped for client and only do 512-bit for servers. There's a much bigger fish to fry which is catching up to ARM.
 
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MS_AT

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Y cruncher
Its memory bound. In particular memory BW bound. You can read the author's blog for more details.

You could go 1024, 2048, 4096 and on and on.
There is a reason to stop at 512b. Picking bigger would have far reaching consequences for the rest of the chip. It's quite obvious if you think in Bytes rather than bits;).

Even with AMD having full AVX-512 units, you can see most of the gains are from the instruction set, not the 512-bit vectors.
But when it hits, it hits hard.

They focused on the one area where Skymont is most deficient, and will see huge improvements in the next couple years (FP/SIMD).
They did not focus on it. They highlighted it. It would be far more unbalanced take if they focused only on the things the chip is good at...
 

Covfefe

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Jul 23, 2025
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They did not focus on it. They highlighted it. It would be far more unbalanced take if they focused only on the things the chip is good at...
Semantics. Call it whatever you want. The fact is they spent 12% of the article by character count discussing how Skymont loses to Zen2 in two specific SIMD heavy benchmarks, and spent 0% of the article on ways that Skymont trounces Zen2.

I appreciate all the deeper testing that chips and cheese does, but it's odd how every time they test Skymont they highlight its deficiencies.
 
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AcrosTinus

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Semantics. Call it whatever you want. The fact is they spent 12% of the article by character count discussing how Skymont loses to Zen2 in two specific SIMD heavy benchmarks, and spent 0% of the article on ways that Skymont trounces Zen2.

I appreciate all the deeper testing that chips and cheese does, but it's odd how every time they test Skymont they highlight its deficiencies.
One might suggest that there is a slight bias towards the red side...
 

MS_AT

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Semantics. Call it whatever you want. The fact is they spent 12% of the article by character count discussing how Skymont loses to Zen2 in two specific SIMD heavy benchmarks, and spent 0% of the article on ways that Skymont trounces Zen2.

If you read the article with attention, you would see that Skymont is shown as somewhat competitive with Zen4, then Zen2 comparison is made to highlight what it is weak at. Skymont is much bigger core (I don't mean mm^2), it has bigger ROB, INT/FP Reg files, more execution units, wider decoder and wider rename. It also probably can sustain higher average clock and cluster vs cluster has more L2. Comparing it to Zen2 for most of the article would be a waste of time.

If your read their Zen5 focused articles they often mention too little of L1i, slow frontend (I mean 4 cycles for a function call, c'mon), too small int register file. Should we say it's odd too?
 

Darkmont

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One might suggest that there is a slight bias towards the red side...
They must be really bad at AMD propaganda then.

"Skymont may not be a P-Core and does not compete for maximum performance. However, it subjectively turns in a good performance in games. I played a variety of games on the Core Ultra 9 285K with affinity set to the 16 E-Cores. All were able to achieve more than playable framerates with few stutters or other issues. It’s a good showcase of what a density optimized core can do on modern process nodes, while also highlighting the issue of diminishing returns when pushing for maximum performance. I suspect a hypothetical chip with just Skymont cores could do quite well in isolation."
1755992027457.png"That doesn’t mean all E-Core chips can go mainstream anytime soon, or that Intel’s E-Core line can displace their P-Cores. If history is anything to go off, an E-Core would need to exceed P-Core performance in a number of applications before it can wear both hats. Long long ago, Intel’s P6-based Pentium M was able to outmatch Netburst-based Pentium 4 chips in a surprisingly large variety of workloads, foreshadowing Intel’s move to ditch Netburst in favor of a beefed up P6 variant in the Core 2 series. Skymont isn’t where Pentium M was in that era, nor does Intel’s Lion Cove P-Core suffer the inefficiencies Netburst did. But there’s no ignoring that Skymont is a very capable core on its own. Intel’s E-Core team deserves credit for packing all that performance into a small area footprint."
 

poke01

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the current Intel e-core still has a long way to go.

Skymont acheived crazy SPEC uplifts because the previous e-core was meh