Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

[Tigerick]

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.





Intel Core Ultra 100 - Meteor Lake



As mentioned by Tomshardware, TSMC will manufacture the I/O, SoC, and GPU tiles. That means Intel will manufacture only the CPU and Foveros tiles. (Notably, Intel calls the I/O tile an 'I/O Expander,' hence the IOE moniker.)

 

[igor_kavinski]

• Threads about upcoming chip leaks, not what the Pentium 4 problems were.

Hey, that qualifies as a personal attack

 

[Josh128]

IIRC Kepler said ~7700X perf so doubt Zen 6C can achieve that with its lower clocks (N3P not N2 like desktop).
Maybe Sony will use custom solution with a shared L2 between CPU and GPU.

PS6 GPU is very weak, based on old game testing as weak or weaker than a Ryzen 1700. Coding to the metal + offloading IO to dedicated logic really pays off.

7700X CPU? Zen 6C will probably be able to achieve that with ~4 to ~4.5 GHz, which shouldnt be a problem on N2.

PS6 GPU vs Ryzen 1700CPU?? Are you conflating CPUs and GPUs?

 

[DavidC1]

View attachment 129034

edit
Test uses B580

Skymont in Gaming Workloads

E-Cores are central in Intel’s CPU strategy.

chipsandcheese.com

Somehow I am not excited should have used 9070XT or 4080

B580 exacerbates the differences between the CPUs because Intel neglected driver optimization on their HD Audi.... I mean HD Graphics. It's at 100+ fps too, meaning it cares more about CPU differences. C&C is the best we got, but this is why I say the modern best is a shadow of the former best such as ixbtlabs, Anandtech, Xbitlabs. Actually, TPU is ok, but they don't go over everything.

From C&C

Skymont isn’t where Pentium M was in that era, nor does Intel’s Lion Cove P-Core suffer the inefficiencies Netburst did.

Lulz. Lion Cove is plenty inefficient. Of course it's not Netburst inefficient, but it's 2025's Netburst. If it was Netburst inefficient, Intel would have zero sales on their desktop parts, and Arrowlake would have underperformed Skylake per clock and used 500W. What do they say? "History doesn't repeat, but rhymes?" And the E core team that made Skymont is going to replace the P core team and design too. I find C&C's Lion Cove fanboyism funny.

Oh, and it's at different clock speeds too.

 

[Magras00]

Couldn't reply directly to #21,202, for some reason spam filter keeps flagging the username.

PS6 uses N3P so this could impact frequencies and matching 7700X with higher memory latencies, -1ghz to boost clocks and less L3 sounds very unlikely. Maybe the Kepler_L2 estimate factors in FF HW offloading (IO logic) otherwise there's no way Zen 6C gets 20-25% higher IPC than Zen 5 desktop. If we're talking 16-32MB full 8 x Zen 6 core config then the figure makes sense.

No I meant CPU. Post was a mess but I've fixed it now.

 

[511]

So by what Metric we would consider Panther Lake a Success?

 

[igor_kavinski]

So by what Metric we would consider Panther Lake a Success?

I think minimum GB6 ST 3300 and MT 15000 (8 cores) would be great starting points.

 

[Magio]

I think minimum GB6 ST 3300 and MT 15000 (8 cores) would be great starting points.

I doubt that MT score is happening with 8 cores, even Apple needs 10 cores to get there and ARL-H needs 14 of them. 15000 could be doable on the 4+4+4 variants, probably.

 

[AcrosTinus]

I think minimum GB6 ST 3300 and MT 15000 (8 cores) would be great starting points.

That is a good base, but 3300 means stagnation.
I would target 3500-ST and 12000-MT, this would feel a lot better.

 

[511]

I think 3000+ ST and 14K-15K multi for the 4+8+4 variant would be better at 30-35W.
As for stagnation I doubt we will get ST Improvements just cause the fact that CGC is LNC+ so expect ~3-5% at best from cores and clock speeds I doubt they can do 5.7 GHz on mobile H series likely to be stuck at 5.4 GHz so expect 5-8% ST improvement.
Just for reference 285H does ~2900 ST so 3000-3100 would be good enough.

ASUSTeK COMPUTER INC. ASUS Zenbook Duo UX8406CA_UX8406CA - Geekbench

Benchmark results for an ASUSTeK COMPUTER INC. ASUS Zenbook Duo UX8406CA_UX8406CA with an Intel Core Ultra 9 285H processor.

browser.geekbench.com

 

[Magio]

I think 3300 would be underwhelming considering the ARM side will do 4000 at better efficiency and Zen6 also most likely will be 3500+, but sadly I think ST will just be underwhelming and 3300 would be fine as damage limitation.

I agree with @511 that 3000+/14+k at OK efficiency would already be nice.

 

[511]

think 3300 would be underwhelming considering the ARM side will do 4000 at better efficiency and Zen6 also most likely will be 3500+, but sadly I think ST will just be underwhelming and 3300 would be fine as damage limitation.

ARM is also using SME for reaching that 4000+ without SME it's around ~3700.

Mac Mini (M4 Pro, High Performance Mode, GB 6.3.0) vs Mac Mini (M4 Pro, High Performance Mode, GB 6.2.2) - Geekbench

 

[Magio]

ARM is also using SME for reaching that 4000+ without SME it's around ~3700.

Mac Mini (M4 Pro, High Performance Mode, GB 6.3.0) vs Mac Mini (M4 Pro, High Performance Mode, GB 6.2.2) - Geekbench

That's true and that's why I'm not saying PTL should outright match them but you'd still want it to keep up a bit better than this or start to at least match them in efficiency.

But that's of course not a realistic outcome for PTL and the minor improvements expected on Cougar Cove. Even further P core improvement seem unlikely to do that, and an unified core is still way too far away to make predictions.

 

[Covfefe]

B580 exacerbates the differences between the CPUs because Intel neglected driver optimization on their HD Audi.... I mean HD Graphics. It's at 100+ fps too, meaning it cares more about CPU differences. C&C is the best we got, but this is why I say the modern best is a shadow of the former best such as ixbtlabs, Anandtech, Xbitlabs. Actually, TPU is ok, but they don't go over everything.

From C&C

Lulz. Lion Cove is plenty inefficient. Of course it's not Netburst inefficient, but it's 2025's Netburst. If it was Netburst inefficient, Intel would have zero sales on their desktop parts, and Arrowlake would have underperformed Skylake per clock and used 500W. What do they say? "History doesn't repeat, but rhymes?" And the E core team that made Skymont is going to replace the P core team and design too. I find C&C's Lion Cove fanboyism funny.

Oh, and it's at different clock speeds too.

Yeah, they did the same thing in their last skymont article.

The overall performance picture though, is that Skymont is still not at the same level as a high performance core. It’s behind in SPEC CPU2017’s integer suite, which represents a favorable set of workloads for a wide core with relatively weak vector execution. In vector-heavy workloads, it’s still hit or miss against Zen 2. Thus Skymont lacks the performance to replace Lion Cove or take on AMD’s best.

Skymont in Desktop Form: Atom Unleashed

Skymont is Intel’s newest E-Core architecture. E-Cores trace their lineage to low power and low performance Atom cores of long ago. But E-Cores have become an integral part of Intel’s h…

old.chipsandcheese.com

I found that Zen2 comparison particularly odd. They focused on the one area where Skymont is most deficient, and will see huge improvements in the next couple years (FP/SIMD). An alternative universe Skymont with a dense 4x512bit FPU could still be under 2mm^2.

 

[511]

are libx264/Y cruncher L3 bound ? cause ARL has the worst L3 design out of all the recent CPUS

 

[Thunder 57]

are libx264/Y cruncher L3 bound ? cause ARL has the worst L3 design out of all the recent CPUS

Neither are to my knowledge. Could be wrong.

 

[DavidC1]

So by what Metric we would consider Panther Lake a Success?

Expected few % faster ST improvements, the MT performance expected out of a 4+8 and Lunarlake level battery life would be considered a success, since if we believe Intel, it should be cheaper.

I think 3300 would be underwhelming considering the ARM side will do 4000 at better efficiency and Zen6 also most likely will be 3500+, but sadly I think ST will just be underwhelming and 3300 would be fine as damage limitation.

You can't expect big performance gains from Pantherlake. Best is Lunarlake efficiency but with 4+8 instead of 4+4.

I found that Zen2 comparison particularly odd. They focused on the one area where Skymont is most deficient, and will see huge improvements in the next couple years (FP/SIMD). An alternative universe Skymont with a dense 4x512bit FPU could still be under 2mm^2.

It isn't even that deficient. Making an efficient use of xtors requires some sacrifices, meaning it'll be slow in some corner case scenarios. You won't make much progress in the next few years by not carefully considering efficiency in every part of design with Moore's Law gains crashing.

Even with AMD having full AVX-512 units, you can see most of the gains are from the instruction set, not the 512-bit vectors. Of course 512-bit is faster, but there's a point where it makes no sense anymore. You could go 1024, 2048, 4096 and on and on. At one point you have to stop. Yes you'll upset some people but you can't please everyone. They should stick to double pumped for client and only do 512-bit for servers. There's a much bigger fish to fry which is catching up to ARM.

 

[MS_AT]

Y cruncher

Its memory bound. In particular memory BW bound. You can read the author's blog for more details.

You could go 1024, 2048, 4096 and on and on.

There is a reason to stop at 512b. Picking bigger would have far reaching consequences for the rest of the chip. It's quite obvious if you think in Bytes rather than bits.

Even with AMD having full AVX-512 units, you can see most of the gains are from the instruction set, not the 512-bit vectors.

But when it hits, it hits hard.

They focused on the one area where Skymont is most deficient, and will see huge improvements in the next couple years (FP/SIMD).

They did not focus on it. They highlighted it. It would be far more unbalanced take if they focused only on the things the chip is good at...