Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

[Tigerick]

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.





Intel Core Ultra 100 - Meteor Lake



As mentioned by Tomshardware, TSMC will manufacture the I/O, SoC, and GPU tiles. That means Intel will manufacture only the CPU and Foveros tiles. (Notably, Intel calls the I/O tile an 'I/O Expander,' hence the IOE moniker.)

 

[adroc_thurston]

When is that expected to be released?

H2'26.
It's PTL IP in a very neatly cost-optimized config. Good.

 

[Joe NYC]

H2'26.
It's PTL IP in a very neatly cost-optimized config. Good.

That's still some time to keep Raptor Lake alive. Who would have thought Intel would still be relying on Raptor Lake after 3, notebook specific CPUS generations were released?
Meteor Lake, Lunar Lake, Panther Lake.

Is it going to be monolithic? Because otherwise, if it has Foveros packaging it will not be that cost optimized.

 

[adroc_thurston]

Who would have thought Intel would still be relying on Raptor Lake after 3, notebook specific CPUS generations were released?

Money.

Meteor Lake, Lunar Lake, Panther Lake.

All woefully cost-inefficient, margin-dilutive parts.

Is it going to be monolithic?

Yea

 

[511]

That's still some time to keep Raptor Lake alive. Who would have thought Intel would still be relying on Raptor Lake after 3, notebook specific CPUS generations were released?
Meteor Lake, Lunar Lake, Panther Lake.

Premium products maybe 4+0+4+4 config would be cheap for PTL

Is it going to be monolithic? Because otherwise, if it has Foveros packaging it will not be that cost optimized.

Yes with N6 PCH

 

[511]

edit
Test uses B580

Skymont in Gaming Workloads

E-Cores are central in Intel’s CPU strategy.

chipsandcheese.com

Somehow I am not excited should have used 9070XT or 4080

 

[511]

 

[igor_kavinski]

On paper, that should mean good I/O and RAM speeds.

 

[511]

Like I said before for the tiles config.

 

[Josh128]

Zen6 core area is quite small, even smaller than Zen4

Why wouldnt it be? People are claiming its a 2 node shrink of Zen 5 core with very minor changes.

 

[511]

Why wouldnt it be? People are claiming its a 2 node shrink of Zen 5 core with very minor changes.

The shrink is still smaller than what Intel got from Intel 7 to N3B(~2X Shrink) vs (1.47) for N4 to N2(P).

 

[OneEng2]

I don't think one should include the 20% shrink from N3 to N2, since I doubt AMD doesn't increase the "architectural" area of the core itself. I don't think core area or CCX area iso core count will change significantly.
But also, Turin Dense saves a good chunk of area because it halves the L3 capacity per core, which Venice Dense reverses.
I agree with your overall sentiment though, the CCD area won't be massive or anything. I think above 150mm2 is a safe guess.

Fair. It is likely that Zen 6 will add logic above and beyond Zen 5. Highly likely IMO. I could go with your ~150mm^2 thoughts.

Where have you heard that Venice D will increase the L3 over Turin D?

You are assuming core area won't be increasing which ain't going to happen also 4X L3 which didn't Shrink

Agreed.

Zen6 core area is quite small, even smaller than Zen4

Do you mean per core Zen 6 on N2 vs Zen 4 on N5?

Why wouldnt it be? People are claiming its a 2 node shrink of Zen 5 core with very minor changes.

It's N4P down to N2 only on desktop. Note, the numbers I gave above were for Turin D which is on N3P. I am assuming that N2 is no more than a 20% transistor density increase over N3P.

As has been pointed out on my estimate (correctly so), Zen 6 will contain more transistors per core, and SRAM doesn't shrink as well as logic gates do... so my original numbers for the CCX for Venice D were likely optimistic.

 

[511]

Zen6 core area is quite small, even smaller than Zen4

Core only or Core+L2 that is the biggest question

 

[coercitiv]

Core only or Core+L2 that is the biggest question

Not quite the thread for this, but AFAIK there aren't changes in L2 size with Z6.

Do we know if Intel intends to change their server tile strategy after DMR? (in the sense of making changes to allow for smaller tiles)

 

[Kepler_L2]

Core only or Core+L2 that is the biggest question

Why would that matter? Both are 1MB L2

 

[fastandfurious6]

Zen6 core area is quite small, even smaller than Zen4

makes sense, 12core ccd

N2 is a major node step over N5/N4/N3

 

[511]

Why would that matter? Both are 1MB L2

I didn't knew the L2 was same

 

[Geddagod]

Zen6 core area is quite small, even smaller than Zen4

I thought they would try to keep area around the same, presumably needed from the Fmax increase. Ig AMD's physical design team just works wonders lol.

All woefully cost-inefficient, margin-dilutive parts.

Grouping PTL in there sounds like a stretch. Intel has been on and on about how PTL will help improve margins significantly once they get it going in volume.

Why wouldnt it be? People are claiming its a 2 node shrink of Zen 5 core with very minor changes.

Shrinks are getting worse and worse, and also tbh I expected a L2 bump

Why would that matter? Both are 1MB L2

This is an unusually small L2 atp, everyone else is using much larger core private caches (Intel, stock arm cores).
Surprising if this ends up being true IMO. Feeding the new core from the same capacity L2 while also likely making the L3 slower, and also increasing the cores dependence on the L2 (simply by the core being faster)... seems unwise.

 

[adroc_thurston]

Grouping PTL in there sounds like a stretch.

Nope.

Intel has been on and on about how PTL will help improve margins significantly once they get it going in volume.

Well, 'significantly'.
Yes, unlike LNL it does not have to deal with MoP or a pile of PMICs, but 18A yields are also not up to par.
Cost will be meh until way into 2026.

 

[511]

Nope

They are eating double margin for Intel even 30-40% for products and 20-30% for foundry(18A and I3 have much better cost and margin than Intel 7) means 50-70% margin combined.
They can do IAA to split that however they want.

 

[Josh128]

I thought they would try to keep area around the same, presumably needed from the Fmax increase. Ig AMD's physical design team just works wonders lol.

Or, 6.5Ghz freq is BS.

 

[igor_kavinski]

Wouldn't it be nice to wake up tomorrow and see a review for:

12P Bartlett Lake

OR

385K Arrow Lake Refresh

OR

388V Panther Lake

OR

Core i3-N405 (all Skymont cores)

 

[511]

Wouldn't it be nice to wake up tomorrow and see a review for:

12P Bartlett Lake

OR

385K Arrow Lake Refresh

OR

388V Panther Lake

OR

Core i3-N405 (all Skymont cores)

You missed 10Ghz Tejas or a P4 on 18A.

 

[igor_kavinski]

You missed 10Ghz Tejas or a P4 on 18A.

That may mean I'm dead and born again in my own reality. A universe inside my own head. And you all are there but actually copies of your real self and not even perfect copies because every one of you is exactly and only as I remember you

 

[Magras00]

Zen6 core area is quite small, even smaller than Zen4

A bit smaller or significantly smaller?

From N4 to N2 SRAM density only scales ~20%. So 48MB L3 will require ~25% more area assuming no design changes like Zen 4 -> Zen 5 area optimisation.

Do we know the area of one Zen 5 vs one Zen 4 core?


Have any leakers confirmed if PS6 goes for 8 Zen 6C + 8MB L3 for cost optimisation or goes all out with 8-12 full Zen 6 cores + 16-48MB L3? IIRC Kepler said ~7700X perf so doubt Zen 6C can achieve that with its lower clocks (N3P not N2 like desktop).
Maybe Sony will use custom solution with a shared L2 between CPU and GPU.

The SW side gains could allow them to get away with weak GPU CPU. Frame extrapolation + input warp for 120FPS. Workgraphs are no joke and could impact everything, smart GPU BVH builders (H-PLOC evolved), GNNs and various ML offloading CPU overhead. Effectively a CPU multiplier.

Even if Sony last minute opts for a Zen 6C CPU ~4ghz that will still be miles ahead of the trash tier PS5 GPU CPU that is weaker than even a 4700H. The 25% higher clocked 4700G only matches 2700X/3600. PS6 GPU CPU is very weak, based on old game testing as weak or weaker than a Ryzen 1700. Coding to the metal + offloading IO to dedicated logic really pays off.

 

[dullard]

Wouldn't it be nice to wake up tomorrow and see...

Yes, that would be nice.

What I really want is to wake up tomorrow and see:

• Threads about performance, not opinions on companies/leadership.
• Threads about upcoming chip leaks, not what the Pentium 4 problems were.
• Threads that are Intel focused that have Intel chips in it. Not page after page of Apple CPUs or the current discussion of Zen6 vs Zen4.
• Threads that are AMD focused that have AMD chips in it.