Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

[Tigerick]

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.





Intel Core Ultra 100 - Meteor Lake



As mentioned by Tomshardware, TSMC will manufacture the I/O, SoC, and GPU tiles. That means Intel will manufacture only the CPU and Foveros tiles. (Notably, Intel calls the I/O tile an 'I/O Expander,' hence the IOE moniker.)

 

[adroc_thurston]

When is that expected to be released?

H2'26.
It's PTL IP in a very neatly cost-optimized config. Good.

 

[Joe NYC]

H2'26.
It's PTL IP in a very neatly cost-optimized config. Good.

That's still some time to keep Raptor Lake alive. Who would have thought Intel would still be relying on Raptor Lake after 3, notebook specific CPUS generations were released?
Meteor Lake, Lunar Lake, Panther Lake.

Is it going to be monolithic? Because otherwise, if it has Foveros packaging it will not be that cost optimized.

 

[adroc_thurston]

Who would have thought Intel would still be relying on Raptor Lake after 3, notebook specific CPUS generations were released?

Money.

Meteor Lake, Lunar Lake, Panther Lake.

All woefully cost-inefficient, margin-dilutive parts.

Is it going to be monolithic?

Yea

 

[511]

That's still some time to keep Raptor Lake alive. Who would have thought Intel would still be relying on Raptor Lake after 3, notebook specific CPUS generations were released?
Meteor Lake, Lunar Lake, Panther Lake.

Premium products maybe 4+0+4+4 config would be cheap for PTL

Is it going to be monolithic? Because otherwise, if it has Foveros packaging it will not be that cost optimized.

Yes with N6 PCH

 

[511]

edit
Test uses B580

Skymont in Gaming Workloads

E-Cores are central in Intel’s CPU strategy.

chipsandcheese.com

Somehow I am not excited should have used 9070XT or 4080

 

[511]

 

[igor_kavinski]

On paper, that should mean good I/O and RAM speeds.

 

[511]

Like I said before for the tiles config.

 

[Josh128]

Zen6 core area is quite small, even smaller than Zen4

Why wouldnt it be? People are claiming its a 2 node shrink of Zen 5 core with very minor changes.

 

[511]

Why wouldnt it be? People are claiming its a 2 node shrink of Zen 5 core with very minor changes.

The shrink is still smaller than what Intel got from Intel 7 to N3B(~2X Shrink) vs (1.47) for N4 to N2(P).

 

[OneEng2]

I don't think one should include the 20% shrink from N3 to N2, since I doubt AMD doesn't increase the "architectural" area of the core itself. I don't think core area or CCX area iso core count will change significantly.
But also, Turin Dense saves a good chunk of area because it halves the L3 capacity per core, which Venice Dense reverses.
I agree with your overall sentiment though, the CCD area won't be massive or anything. I think above 150mm2 is a safe guess.

Fair. It is likely that Zen 6 will add logic above and beyond Zen 5. Highly likely IMO. I could go with your ~150mm^2 thoughts.

Where have you heard that Venice D will increase the L3 over Turin D?

You are assuming core area won't be increasing which ain't going to happen also 4X L3 which didn't Shrink

Agreed.

Zen6 core area is quite small, even smaller than Zen4

Do you mean per core Zen 6 on N2 vs Zen 4 on N5?

Why wouldnt it be? People are claiming its a 2 node shrink of Zen 5 core with very minor changes.

It's N4P down to N2 only on desktop. Note, the numbers I gave above were for Turin D which is on N3P. I am assuming that N2 is no more than a 20% transistor density increase over N3P.

As has been pointed out on my estimate (correctly so), Zen 6 will contain more transistors per core, and SRAM doesn't shrink as well as logic gates do... so my original numbers for the CCX for Venice D were likely optimistic.

 

[511]

Zen6 core area is quite small, even smaller than Zen4

Core only or Core+L2 that is the biggest question

 

[coercitiv]

Core only or Core+L2 that is the biggest question

Not quite the thread for this, but AFAIK there aren't changes in L2 size with Z6.

Do we know if Intel intends to change their server tile strategy after DMR? (in the sense of making changes to allow for smaller tiles)

 

[Kepler_L2]

Core only or Core+L2 that is the biggest question

Why would that matter? Both are 1MB L2

 

[fastandfurious6]

Zen6 core area is quite small, even smaller than Zen4

makes sense, 12core ccd

N2 is a major node step over N5/N4/N3

 

[511]

Why would that matter? Both are 1MB L2

I didn't knew the L2 was same