Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

[Tigerick]

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.





Intel Core Ultra 100 - Meteor Lake



As mentioned by Tomshardware, TSMC will manufacture the I/O, SoC, and GPU tiles. That means Intel will manufacture only the CPU and Foveros tiles. (Notably, Intel calls the I/O tile an 'I/O Expander,' hence the IOE moniker.)

 

[H433x0n]

That's my problem with Intel's approach. Instead of refining Intel 4 (and they already failed on it with MTL-S),

How? It’s in HVM right now in Ireland. We don’t know any of the performance characteristics so we can’t make any definitive judgements.

they will tackle a new node and new architecture at the same with ARL-S on Intel 20A. Sounds like a recipe for delay/disaster. At least this time, maybe they will still get to release the CPU on time by using N3 so it might be the first ever iso-process battle between Intel and AMD, at least for the compute tiles. The best comparison would be if AMD were to use IFS for their entire CPU package and with Intel not holding back any fab advantage for themselves.

The intel 4 / 3 & Intel 20A / 18A are two programs running in parallel and they’ll be in volume production at different fabs.

 

[Geddagod]

(and they already failed on it with MTL-S)

I mean I just said this, but even if Intel 4 clocked as high as Intel 7 Ultra off the bad, it's still highly unlikely that they would have gotten to RPL-S level clock speeds. For a couple reasons really, which I have listed before but am going to reiterate:

• Lower fin count
• less DTCO improvements
• architecture tweaks making it harder to clock higher (changes with the L1)

Idk why so many people are whining about MTL clock speeds when Intel has always stagnated frequency even when their nodes were executing pretty well, as I listed above in my previous reply.
Also, how serious was Intel ever about releasing MTL-S? Their rumored highest core count sku was 6+16. That's nowhere near a flagship sku. At best I think it was gonna be a "low end" desktop option launching a bit earlier than ARL, while being branded as the same generation.

they will tackle a new node and new architecture at the same with ARL-S on Intel 20A. Sounds like a recipe for delay/disaster.

You have to take risks if you want to get back in the lead. Intel goes too conservative, people complain about them not being innovative enough. Intel takes risks, people blame them for trying to do too much at once. lol.

At least this time, maybe they will still get to release the CPU on time by using N3 so it might be the first ever iso-process battle between Intel and AMD, at least for the compute tiles

Zen 5 isn't using N3 except for the dense core skus apparently

 

[igor_kavinski]

How? It’s in HVM right now in Ireland.

I was referring to the canned desktop CPU.

 

[Hulk]

That's my problem with Intel's approach. Instead of refining Intel 4 (and they already failed on it with MTL-S), they will tackle a new node and new architecture at the same with ARL-S on Intel 20A. Sounds like a recipe for delay/disaster. At least this time, maybe they will still get to release the CPU on time by using N3 so it might be the first ever iso-process battle between Intel and AMD, at least for the compute tiles. The best comparison would be if AMD were to use IFS for their entire CPU package and with Intel not holding back any fab advantage for themselves.

While the way you are looking at the situation is entirely valid it could also be viewed from another perspective, which is equally valid.

Intel didn't fail with MTL-S so much as they over-achieved with Intel 7 with the development through ADL, RPL, and RPL-R, which pushed clocks into the stratosphere in order to remain competitive with AMD in terms of pure performance. They were in the same position with the Haswell Refresh (Devils Canyon) with Broadwell. This is "Broadwell 2.0" Like it or not when Intel refines a node to the point where they can achieve really great clocks, even at the expense of efficiency, they go for it. That's just Intel and how they operate.

Also, it may seem like Intel is taking on a lot with a new node and architecture with ARL-S but in reality they are taking on even more with Meteor Lake. Meteor is the first 4 die Foveros client part in mass production. If you consider the graphics tile to be "known" technology from their ARC line of GPU's then the only new tile on ARL-S is the CPU tile, everything else has been in production. They only needs get yields up on one tiny CPU tile.

 

[Thibsie]

While the way you are looking at the situation is entirely valid it could also be viewed from another perspective, which is equally valid.

Intel didn't fail with MTL-S so much as they over-achieved with Intel 7 with the development through ADL, RPL, and RPL-R, which pushed clocks into the stratosphere in order to remain competitive with AMD in terms of pure performance. They were in the same position with the Haswell Refresh (Devils Canyon) with Broadwell. This is "Broadwell 2.0" Like it or not when Intel refines a node to the point where they can achieve really great clocks, even at the expense of efficiency, they go for it. That's just Intel and how they operate.

Also, it may seem like Intel is taking on a lot with a new node and architecture with ARL-S but in reality they are taking on even more with Meteor Lake. Meteor is the first 4 die Foveros client part in mass production. If you consider the graphics tile to be "known" technology from their ARC line of GPU's then the only new tile on ARL-S is the CPU tile, everything else has been in production. They only needs get yields up on one tiny CPU tile.

Over-achieving with Intel7 ?
You mean, the renamed 10nm they dragged for years and finally got right? I wouldn't call it that way.

 

[eek2121]

If Intel is anywhere close to 4ghz this early, I don’t believe any of the rumors of a large frequency regression. I always believed we would see a small one for single core clocks, but a large improvement in multicore clocks. I would be shocked it production silicon was any slower than 5.5ghz.

I am confused as to why anyone thinks MTL-S is a failure. Intel and AMD both cancel projects all the time. Raptor Lake Refresh likely has higher margins and will still sell great. They likely can produce the chips in higher volumes as well.

On the mobile side, clocks are in line with AMD’s best (except the 7945hx which is technically a desktop chip), so Meteor Lake as a whole does not look like a failure to me.

So if Meteor Lake has a bit better IPC than Raptor Lake, Raptor Lake is already slightly ahead of Zen 4, and clocks are equal or better, the chip will be faster than AMD’s best (again, except the 7945hx)

I also would not rule out a 5.4ghz SKU.

The real question that needs to be answered is perf/watt.

 

[Hulk]

Over-achieving with Intel7 ?
You mean, the renamed 10nm they dragged for years and finally got right? I wouldn't call it that way.

Totally valid POV. This is why we discuss.

 

[Hulk]

Tested my 13600K today. This chart illustrates how more transistors increases efficiency assuming equal architectures and fabrication. It's another way of showing the v/f curve is not linear.

 

[Abwx]

Tested my 13600K today. This chart illustrates how more transistors increases efficiency assuming equal architectures and fabrication. It's another way of showing the v/f curve is not linear.

View attachment 86751

It s not more transistors per se that increase efficency, it s more cores.

If you double the core amount you can reduce frequency by a 2 factor and power per core will be reduced by a 4 factor, so with 2x the core amount at 0.5x the frequency you ll get the same throughput at 0.5x the power.

Now doubling the transistor count in a core wouldnt produce the same result at all.

 

[Hulk]

It s not more transistors per se that increase efficency, it s more cores.

If you double the core amount you can reduce frequency by a 2 factor and power per core will be reduced by a 4 factor, so with 2x the core amount at 0.5x the frequency you ll get the same throughput at 0.5x the power.

Now doubling the transistor count in a core wouldnt produce the same result at all.

Except that I stated "same architecture." The only way to increase transistors for the same architecture is to add more cores! Yes, I could have communicated that more effectively by simply stating "more cores."
Point taken. Thanks for the correction.

 

[igor_kavinski]

The only way to increase transistors for the same architecture is to add more cores!

Or increase L2/L3 cache or even introduce a unified mega L4 cache.

 

[Hulk]

Or increase L2/L3 cache or even introduce a unified mega L4 cache.

Corrected again!

 

[H433x0n]

Source

Proper test comparing 13700H against 7840HS. MTL doesn’t have to improve things that much to take the mobile power efficiency advantage.

Edit: Really wish they they equalized the memory speeds so that they both ran DDR5-5600 at identical timings. It was so close that if the 13700H had DDR5-5600 it could’ve tipped the scales closer at 50W.

 

[naukkis]

Source

Proper test comparing 13700H against 7840HS. MTL doesn’t have to improve things that much to take the mobile power efficiency advantage.

Difference is more than massive. At mobile TDP levels 8-core 7840 has up to 30% more multicore performance than 14-core hybrid Intel 13700H. AMD can too, even in current generation add cores and use more efficient C-cores to improve efficiency.

 

[H433x0n]

Difference is more than massive. At mobile TDP levels 8-core 7840 has up to 30% more multicore performance than 14-core hybrid Intel 13700H. AMD can too, even in current generation add cores and use more efficient C-cores to improve efficiency.

The 7840HS had better memory and squeaked out a 3% win at 50W and that’s a massive difference? Were we watching the same video?

 

[TESKATLIPOKA]

The 7840HS had better memory and squeaked out a 3% win at 50W and that’s a massive difference? Were we watching the same video?

CB R23 doesn't look very good.


edit:
At 40W difference is 27%.
At 45W difference is 20%.
At 50W difference is 16%.
At 55W difference is 13%.
A big difference even though Intel has a lot more cores, which helps massively with efficiency.
Meteor Lake would need to have ~20% higher clocks at 40W depending on IPC gain to be on par with Phoenix.
Will that happen? We will see.

 

[naukkis]

The 7840HS had better memory and squeaked out a 3% win at 50W and that’s a massive difference? Were we watching the same video?

14-core cpu should have big efficiency benefit against 8-core one when offering similar performance. Yet that 14-core cpu loses efficiency race.

 

[H433x0n]

14-core cpu should have big efficiency benefit against 8-core one when offering similar performance. Yet that 14-core cpu loses efficiency race.

We’re comparing a DUV based Intel 7 process against TSMC N4. Of course it will have an efficiency advantage.

It’s way closer than I thought it’d be.

 

[Henry swagger]

Source

Proper test comparing 13700H against 7840HS. MTL doesn’t have to improve things that much to take the mobile power efficiency advantage.

Edit: Really wish they they equalized the memory speeds so that they both ran DDR5-5600 at identical timings. It was so close that if the 13700H had DDR5-5600 it could’ve tipped the scales closer at 50W.

Good performance by the 13700h on a older bigger process.. meteor will have better efficiency than this ✅🏅

 

[tamz_msc]

Has this been posted? Looks promising if it turns out to be true.

Alleged Intel Arrow Lake-S CPU Power Limits Revealed: 125W PL1, 177W PL2, 333W PL4 For 8+16 Core Unlocked SKU

Alleged power limits of Intel's Arrow Lake-S Desktop CPU featuring 8 P-Cores and 16 E-Cores have been revealed by Darkmont.

wccftech.com

 

[Hulk]

Good performance by the 13700h on a older bigger process.. meteor will have better efficiency than this ✅🏅

Intel claims 40% improved efficiency for Intel 4 vs Intel 7 at ISO frequency/20% better performance at ISO power. The question is at what ISO frequency/power? As usual I suspect we are going to have to very competitive parts from Intel and AMD in the mobile segment.

Also since the entire CPU complex is located on one tile I have a suspicion latency is going to be better than we might be thinking on Meteor.

 

[AMDK11]

If NovaLake is 16+32, I suspect there may be 8 P cores + a unit for rent. It would fit the codename.

 

[Hulk]

How? It’s in HVM right now in Ireland. We don’t know any of the performance characteristics so we can’t make any definitive judgements.


The intel 4 / 3 & Intel 20A / 18A are two programs running in parallel and they’ll be in volume production at different fabs.

If Intel is running 20A and Intel 3 in parallel I would assume they each have advantages and disadvantages or they would be going with one or the other? Why do you think these nodes are running in parallel production?

 

[Hulk]

If NovaLake is 16+32, I suspect there may be 8 P cores + a unit for rent. It would fit the codename.

Warning. Controversial thoughts below due to the lack of CPU news and the agonizing wait for Raptor Refresh, Meteor Lake, Zen 5, ...

I don't think Intel is going to manufacture parts with more than 8 P cores for client moving forward. It just doesn't make sense when for a given die area the E's would be more useful than additional P's. Also I agree with the rumors that HT is going away. If there is going to be a continued pursuit by Intel to hybrid CPU's, which appears to be the case based on everything we know so far, then Intel might as well go "all in."

"All in" would mean removing HT from the P's and spending those transistors on increasing ST performance in the big cores and/or adding more E cores This starts to look more tempting when you get to the point of having 32 or more E cores, which could achieve a score of nearly 40,000 in CB R23 on their own.

I realize many people don't buy into the "area efficiency" for the E's and the rationale for the hybrid approach. I also understand that while Intel's philosophy may be sound on paper there is still work to do in practice, namely the Thread Director more "correctly" allocating resources. So these E haters to have a point currently for some rare applications here and there.

All this being said I'm a fan of both AMD and Intel, or more correctly stated the technology in general. But if Intel does reach process parity with AMD in the near future then AMD will have to resort to hybrid architecture to remain competitive. The alternative is that they will have to stay with P cores only parts but need to put so many of them (P cores) on the die that it will hurt them economically.

Consider a hypothetical 8+32 Raptor Lake part (yes I know that will never exist I'm just using it as an example of cores whose performance we are familiar. In the desktop client space it would be hard to imagine a situation where that wouldn't be enough MT compute. And by enough I don't mean enough compute (as we can never have enough). What I mean by enough if enough, for that market segment. If more than 8+32 MT is required then the user should be looking upmarket at Xeon/Threadripper class parts.

 

[H433x0n]

If Intel is running 20A and Intel 3 in parallel I would assume they each have advantages and disadvantages or they would be going with one or the other? Why do you think these nodes are running in parallel production?

I think there’s more than 2 running in parallel, I’m pretty sure 16A is in technology development at the moment too.

It’s what you’ve got to do to keep these projects running at a 24 month release cycle. They get broken down into stages, where different teams work on them at different points in the development lifecycle.