Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

[Tigerick]

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.





Intel Core Ultra 100 - Meteor Lake



As mentioned by Tomshardware, TSMC will manufacture the I/O, SoC, and GPU tiles. That means Intel will manufacture only the CPU and Foveros tiles. (Notably, Intel calls the I/O tile an 'I/O Expander,' hence the IOE moniker.)

 

[dullard]

PTL U will be a regression in most of those. It'd be quite surprising if it somehow retains the battery life gains from LNL

So, you are claiming that the first chip below will lose on performance and battery life:

A) 15 W panther lake U chip with 4 P cores and 4 E cores on a smaller / newer node, with RibbonFET which increases power efficiency, and PowerVia that increases power efficiency

vs

B) A 15 W lunar lake chip with 4 P cores and 4 E cores

If so, why on Earth would Intel develop and launch such an inferior chip when they already have a good one?

 

[511]

Considering this is the first time in god knows how long there's actual excitement for an Intel mobile platform I think Intel would be fools not to have a successor to it eventually. It makes sense that PTL won't have one as the plans for that were set in stone long before they knew how LNL would turn out, but going onto NVL they really ought to bring back the V series.

I think many improvement in LNL will be carried forward like the IMC design with CPU Cores SLC
I think PMIC will be optional like with MTL-U the clock speed granularity choice on package memory will not be carried forward

A 4P + 6/8 Arctic Wolf + Celestial (or newer) GPU and the general LNL design choices on 18A or even 18A-P (which they've already said would be optimized for mobile) sounds feasible and would b a dream chip for thin and lights.

Yes if Arctic wolf is another 30% like skymont

 

[511]

So, you are claiming that the first chip below will lose on performance and battery life:

A) 15 W panther lake U chip with 4 P cores and 4 E cores on a smaller / newer node, with RibbonFET which increases power efficiency, and PowerVia that increases power efficiency

vs

B) A 15 W lunar lake chip with 4 P cores and 4 E cores

If so, why on Earth would Intel develop and launch such an inferior chip when they already have a good one?

I agree outside of GPU (4 Xe3 Cores) and l5-10% hit in battery life there won't be much difference

 

[igor_kavinski]

If so, why on Earth would Intel develop and launch such an inferior chip when they already have a good one?

My personal suspicion is that using on-package RAM was not without its issues and Intel didn't enjoy that experience hence there won't be such a successor. OEMs may also have complained because LNL reduces one component over which they could compete on price by buying up RAM chips in volume. ISO speed of the on-package RAM also makes it hard for the OEMs to differentiate their designs from that of competitors and they prefer the flexibility of using faster or slower RAM to hit different price points.

 

[cebri1]

So the famed E core with so many changes and massive area increase is still at ~Skylake IPC in Specint? What happened? Is it downclocking due to some power savings on the test machine? Lion Cove gets blasted for it's large area, but at least it delivered the 10-15% ipc, but the E core seems like it's not even reaching half of what was promised. Intel said the ring version is only around 5% better, or 5-10% better than a decade old P core...

lol, comparing Crestmont with 24MB of L3 vs Skymont with 4MB of L2. It’s a massive jump.

 

[cannedlake240]

why on Earth would Intel develop and launch such an inferior chip when they already have a good one?

It'll be a 15W Intel U series chip as usual, so a higher volume part. It does borrow from LNL, and it'll be more efficient than MTL/ARL

comparing Crestmont with 24MB of L3 vs Skymont with 4MB of L2. It’s a massive jump.

I doubt the jump from Skymont LP to ARL Skymont will be as large as the jump between MTL atoms. Skymont LP has a 4mb L2, SLC and much lower memory latency than CMT-LP. It's unfortunate they had to sacrifice L1D latency for clocks when Apple and Arm have been increasing clocks without the tradeoff. Especially when Intel L3 and atom cluster L2 are already quite slow

 

[OneEng2]

TSMC N3B density is around ~197 MTr/mm2. N3E is around ~185 (after regression).

Intel 3 is around ~145. So, a 30% will put 18A around ~185. This puts 18A very much on par with N3E.

Since, N2 is expected to be 10% to 15% better than N3E, naturally N2 will be better than 18A by the same amount in density. But, 18A with BSPDN is expected to offer more performance than N2.

According to what I have read, there are other advantages that GAA and BSPD provide in flexibility of design that may well contribute to the overall picture of chip performance and density in a more favorable light than the raw metrics may suggest.

I have a feeling AMD is chasing Intel for high clock speeds and paying the price for it. It means the modern AMD chips are prioritized for higher clocks and sacrifice low clock efficiency.

Possibly so; however, Higher overall performance is more important in most high profit markets. Where absolute performance ISN'T the biggest design constraint in the market, it is generally performance within a power envelope. I assume in your statement that you feel that Intel's Lunar Lake core is besting Zen 5 in the ultra light laptop market. AMD's design choices may be better suited to the data center where profits are much higher. Just a thought.

Since when is a 232mm2 die on N4P cheap?

Fair enough; however, one could argue that AMD should be using chiplets to avoid the yield issues and expense of the large monolithic die, but lets not be to clever by half here. Lunar Lake's compute tile alone is 140mm sq. It looks to be North of 200 mm sq total. Packaging is not free, nor is it free to produce the other 2 chips in the design.

For desktop and data center chips, AMD's design choices may look better. We will see soon enough.

That 80% market share in client means nothing for the orders from TSMC, and the entire Arrow Lake is now made of TSMC dies.

Intel is not getting pricing that is any better than AMD or Qualcomm. If anything, Intel's pricing is worse. Intel already announced it wants to shift production away from TSMC, so TSMC has zero incentive to offer Intel favorable pricing.

Given the fact that Arrow Lake is on N3B, for the CPU die while Zen 5 is N4P, Arrow Lake is on more expensive node and is also using more expensive packaging.

In short, no economies of scale, and cost disadvantage vs. Zen 5.

AMD likely has a disadvantage in the use of a single monolithic die in the mobile market (I am guessing yield, but certainly die per wafer) vs Lunar Lake compute tile; however, things may look quite different in the desktop and data center products (or even non "thin and light" laptop market that is 60-70% of the laptop market).

 

[jpiniero]

Keep in mind the vast majority of Intel's client sales in 2025 will be Raptor and Bartlett. Probally 2026 too.

 

[DavidC1]

So, you are claiming that the first chip below will lose on performance and battery life:

A) 15 W panther lake U chip with 4 P cores and 4 E cores on a smaller / newer node, with RibbonFET which increases power efficiency, and PowerVia that increases power efficiency

Battery life is a matter of reaching low idle power and staying there as long as possible, which process doesn't really help because unlike the day of Pentium III 25 years ago, the CPUs in notebooks already reach lowest power states very frequently. Process mostly helps when CPU is active.

Also RibbonFET/PowerVia is much smaller of a gain in process. When they went from 32nm to 22nm with Ivy Bridge, there was no gain in battery life. It was Haswell that brought a big gain, because it actually addressed those issues.

I'm pretty sure Pantherlake will do better on performance. But battery life against Lunarlake? Don't bet on it. Already Dell doesn't have a successor to Lunarlake.

If so, why on Earth would Intel develop and launch such an inferior chip when they already have a good one?

Because they are run by finance. Why do you think they didn't get Celeron out until Cyrix/AMD? What about Pentium M and Transmeta? Lunarlake and Apple? They are all reactionary, because it maximizes margins and revenue.

 

[adroc_thurston]

why on Earth would Intel develop and launch such an inferior chip when they already have a good one?

I know this is like 6d chess thinking by ~here~ standards, but good stuff is gooder when cheaper. LNL is a very very expensive tablet toy, not suitable for real world™ laptop segments.
You can very clearly see it on that leaked Dell roadmap etc.

 

[Joe NYC]

AMD likely has a disadvantage in the use of a single monolithic die in the mobile market (I am guessing yield, but certainly die per wafer) vs Lunar Lake compute tile; however, things may look quite different in the desktop and data center products (or even non "thin and light" laptop market that is 60-70% of the laptop market).

Lunar Lake is mostly monolithic with a small IO die.
Arrow Lake has more tiles, so only CPU Tile is on the most advanced node, other tiles are on less expensive nodes.
But both have an overhead of more expensive packaging.

In mainstream market next year, it will be ~170 mm2 Kraken on N4P.
Lunar Lake at ~170 mm2 N3B + IO die + packaging

So Lunar Lake will be priced out of mainstream marked due to high cost. It will be only a premium MacBook Air competitor. Intel could, in theory, try to increase the size of this market by persuading customers it is worthwhile to spend extra ~ $300 on their laptop. We will see how it plays out.

 

[dullard]

I know this is like 6d chess thinking by ~here~ standards, but good stuff is gooder when cheaper. LNL is a very very expensive tablet toy, not suitable for real world™ laptop segments.
You can very clearly see it on that leaked Dell roadmap etc.

Seems like I really touched a nerve with my post, judging by the number of people replying. And judging by how many people think a Dell XPS-only and also 28 W to 90 W only roadmap is relevant to a 15 W Panther Lake - U CPU. It would be so much more relevant if someone leaked Dell's 15 W thin and light roadmaps.

So we have posts of:

• Panther Lake - U will be worse than Lunar Lake performance and battery life
• Panther Lake - U is reactionary like Celeron
• Panther Lake - U is good solely because it is cheaper

Anyone else with Panther Lake - U predictions?

 

[cannedlake240]

Lunar Lake is mostly monolithic with a small IO die.
Arrow Lake has more tiles, so only CPU Tile is on the most advanced node, other tiles are on less expensive nodes.
But both have an overhead of more expensive packaging.

In mainstream market next year, it will be ~170 mm2 Kraken on N4P.
Lunar Lake at ~170 mm2 N3B + IO die + packaging

So Lunar Lake will be priced out of mainstream marked due to high cost. It will be only a premium MacBook Air competitor. Intel could, in theory, try to increase the size of this market by persuading customers it is worthwhile to spend extra ~ $300 on their laptop. We will see how it plays out.

It's 140 not 170mm2 lol that's not a small difference. It's NPU is too large which apparently is fixed by the 5th gen IP. All 3 IPs are too large on LNL, it could've been a 120mm2 chip easily if LionCove, Xe2 and NPU were more space efficient

 

[Joe NYC]

It's 140 not 170mm2 lol that's not a small difference. It's NPU is too large which apparently is fixed by the 5th gen IP. All 3 IPs are too large on LNL, it could've been a 120mm2 chip easily if LionCove, Xe2 and NPU were more space efficient

Which one is 140 mm2, Kraken or LNL?

Edit: Looks like Lunar Lake is:
Compute die: 140 mm2
IO die: 46 mm2

 

[cannedlake240]

Seems like I really touched a nerve with my post, judging by the number of people replying (and how many people think a Dell XPS-only 28 W to 90 W roadmap is relevant to a 15 W Panther Lake - U CPU).

So we have posts of:

• Panther Lake - U will be worse than Lunar Lake performance and battery life
• Panther Lake - U is reactionary like Celeron
• Panther Lake - U is good solely because it is cheaper

Anyone else with Panther Lake - U predictions?

No need for predictions lol its not a -V/MX series chip that goes all out on efficiency. The Celeron is counterpart already exists it's called Wildcat lake on 18A.

 

[poke01]

Anyone else with Panther Lake - U predictions?

Yep, PTL-U will be better in every way cost, performance and core count than LNL.
It will only lose in idle.

I’m not saying PTL-U is bad. What most are saying restricting LNL design to a 4+4 but I see why Intel did that. A 6+8 or 8+8 would have gotten very expensive on N3B, probably over $2000 at that point most would get a laptop with RTX or a MacBook. Maybe Intel can try again in 4 years time using their own nodes.h

 

[dullard]

Yep, PTL-U will be better in every way cost, performance and core count than LNL.
It will only lose in idle.

I've only seen rumors of 4 P + 4 LPE for PTL-U. Have you seen anything different?

As for 6+6 or more, I just don't see the market for it. As you said, it would be even more expensive and who really needs that many cores in a thin and light laptop (especially since in the 15 W range, all those cores would all be even more power constrained and thus even slower frequencies)? The few people who would want that combination just don't seem to make a sufficient market to me.

 

[adroc_thurston]

Seems like I really touched a nerve with my post

You're just being not very smart.

Panther Lake - U will be worse than Lunar Lake performance and battery life

Perf no, BL yes.

Panther Lake - U is good solely because it is cheaper

YES. and NVL-U is even cheaper than that!
This isn't GPGPU or even big boy server CPU where prices are arbitrary. Client margins are tight, and laptop cost structure means SoC cost bumps hurt. a lot.

 

[Joe NYC]

It's 140 not 170mm2 lol that's not a small difference. It's NPU is too large which apparently is fixed by the 5th gen IP. All 3 IPs are too large on LNL, it could've been a 120mm2 chip easily if LionCove, Xe2 and NPU were more space efficient

Time to market is also important variable. If the optimizations you mention delayed Lunar Lake by 6+ months (and I don't even know if LionCove can be slimmed down), Lunar Lake would end up with a less impact in the market place, so it was probably a good decision.

It seems that Strix Halo may also be released with sub optimal die area optimization, on expensive node, in order to achieve good time to market.

 

[511]

Lunar Lake is mostly monolithic with a small IO die.
Arrow Lake has more tiles, so only CPU Tile is on the most advanced node, other tiles are on less expensive nodes.
But both have an overhead of more expensive packaging.

In mainstream market next year, it will be ~170 mm2 Kraken on N4P.
Lunar Lake at ~170 mm2 N3B + IO die + packaging

IO is N6 which is dirt cheap and 46 mm2 iirc also 140mm2 also yield is exponential so it will be possible that N3B is yielding Better for LNL die vs N4P strix point

So Lunar Lake will be priced out of mainstream marked due to high cost. It will be only a premium MacBook Air competitor. Intel could, in theory, try to increase the size of this market by persuading customers it is worthwhile to spend extra ~ $300 on their laptop. We will see how it plays out.

No one can charge prices like apple but i guess Ultra 5 will be fine for most users at ~$1050 like asus probook

 

[dullard]

You're just being not very smart.

No need for personal attacks when I ask a few questions.

 

[adroc_thurston]

No need for personal attacks when I ask a few questions.

Wasn't meant to be, it's just everything that could be said about laptop SoC costs has already been said. Cheaper *is* better.

 

[poke01]

there’s no point beating the bush. PTL-U is better for OEMs and for Intel. We will have to wait for PTL reviews. But like others said Intel has bigger things to worry about.

 

[cannedlake240]

Yep, PTL-U will be better in every way cost, performance and core count than LNL.
It will only lose in idle.

I’m not saying PTL-U is bad. What most are saying restricting LNL design to a 4+4 but I see why Intel did that. A 6+8 or 8+8 would have gotten very expensive on N3B, probably over $2000 at that point most would get a laptop with RTX or a MacBook. Maybe Intel can try again in 4 years time using their own nodes.h

PTL max out at 4+8. Wonder how much it'll regress in dgpu gaming vs ARL and MTL. Can low latency communication on E cores salvage PTL gaming perf? They shouldve refreshed the 6+8 MTL CPU tile too if ARL N3 is proving too expensive

 

[Doug S]

Pick the higher wattage charger you have, and let it charge the Mac for 24 hours (or more). I didn't use my M1 for almost two years and that's what I had to do (though with the Apple charger).
Same happened with the Mac I got at work (except I think it had been staying in storage for more than 2 years).

Supposedly if a lithium battery is allowed to fully self discharge when it is eventually charged it is supposed to be charged extremely slowly back to full, or it will greatly compromise the battery's future life. Self discharge down to zero is about the worst thing you can do to them. Maybe the Mac has some way of figuring out if the battery ran down to flat due to usage or due to self-discharge, and has a very super slow charge algorithm for that case and won't let you try to power it on until that's complete?

I'd be interested to hear whether "plug it in for a day or two" can revive Igor's M1.