Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

[Tigerick]

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.





Intel Core Ultra 100 - Meteor Lake



As mentioned by Tomshardware, TSMC will manufacture the I/O, SoC, and GPU tiles. That means Intel will manufacture only the CPU and Foveros tiles. (Notably, Intel calls the I/O tile an 'I/O Expander,' hence the IOE moniker.)

 

[H433x0n]

PTL max out at 4+8. Wonder how much it'll regress in dgpu gaming vs ARL and MTL. Can low latency communication on E cores salvage PTL gaming perf? They shouldve refreshed the 6+8 MTL CPU tile too if ARL N3 is proving too expensive

Why would it regress in dGPU gaming performance compared to ARL & MTL?

 

[DavidC1]

• Panther Lake - U is reactionary like Celeron
• Panther Lake - U is good solely because it is cheaper

I am the one that said Intel is reactionary, and the reactionary chip is Lunarlake. This reaction is good, except it'll end there. The smart thing they should have done is do it 2 decades ago, so they would have a good product in the first place. That's called being proactive, which doesn't exist for Intel.

Intel as a whole company has NEVER been proactive in anything. That's why constant threat of entire company going under happens every so often. If they were actually proactive, they would have had the entire computing market right now, Android, iOS, Windows, everything. It is their refusal to be proactive why Smartphone threat to their dominance exists. It is why WoA and Apple Mx threat exists.

Instead of having no direct successor to Lunarlake, they should make a successor that tries to one-up Lunarlake that does even better on battery life department.

The cherry on top to this is the government and lawyers always handing Intel favors and not blowing open the x86 license decades ago.

 

[DavidC1]

One thing to keep in mind with the L1 latency discussion, x86 cores clock higher, so the real latency is closer than the latency in cycles.

L1d size and latency

	M3 - performance core	X Elite - Oryon	Lunar Lake - Lion Cove	Strix Point - Zen5
size	192 KB	128 KB	48 KB 192KB	48 KB
latency (cycles)	3 cycles	3 cycles	4 cycles 9 cycles	4 cycles
core max clock speed	4.05 GHz	3.8 - 4.2 GHz	4.5 - 5.1GHz	5.0 - 5.1 GHz
latency (nanoseconds)	0.74 ns	0.79 - 0.71 ns	0.88 - 0.78 ns 2 - 1.76 ns	0.8 - 0.78 ns

That's the whole point though. You gain enormous efficiency benefits by aiming for lower clocks. The cache size difference is still there, even if you normalize to absolute latency.

By doing that you save on power, you save cell size thus you get smaller chip out of it, thus it's easier to manufacture and produce. And it serves Server and Laptop markets well.

Apple is incredibly ahead in the efficiency department. Actually ARM in general is ahead too. Remember the people saying ARM couldn't reach PC chip performance? Well, that claim was BS as people saying x86 can't reach ARM chips in efficiency. The difference is the mindset, and the execution capability of the team.

The latest ARM cores in computers that fit in the pocket have performance per clock way better than both Lion Cove and Zen 5.

The fact that the two teams within Intel itself is wildly different in capability should tell you this. x86 can do better, much better!

 

[AcrosTinus]

That's the whole point though. You gain enormous efficiency benefits by aiming for lower clocks. The cache size difference is still there, even if you normalize to absolute latency.

By doing that you save on power, you save cell size thus you get smaller chip out of it, thus it's easier to manufacture and produce. And it serves Server and Laptop markets well.

Apple is incredibly ahead in the efficiency department. Actually ARM in general is ahead too. Remember the people saying ARM couldn't reach PC chip performance? Well, that claim was BS as people saying x86 can't reach ARM chips in efficiency. The difference is the mindset, and the execution capability of the team.

The latest ARM cores in computers that fit in the pocket have performance per clock way better than both Lion Cove and Zen 5.

The fact that the two teams within Intel itself is wildly different in capability should tell you this. x86 can do better, much better!

This strange obsession with ARM IPC is beyond me, there are two approaches to Core performance. You can go wide with less stages and lower clockspeed and get high performance or go less wide more stages and high clockspeed for high performance. Each approach has its pros and cons. X86 has the IO, expandability and software support advantage and as someone that does stuff with their system, this is the most important to me.

Wake me up when Apple has a Mac with an actual GPU or a PCIe slot and support for expansions cards. The Ampere workstation is a joke compared to Threadripper or Xeon as well.

 

[cannedlake240]

Why would it regress in dGPU gaming performance compared to ARL & MTL?

Because it only has 4P/4T vs ARL 6P and MTL 6P/12T? Wouldn't that bottleneck a 5080 mobile that PTL laptops will be paired with?

 

[mikk]

Panther Lake has 8 Darkmont cores on the ringbus, there are not only 4 cores for gaming. SMT isn't necessarily better for gaming workloads. On Skymont and newer E cores should be more performant than SMT. Also Panther Cove is getting the IMC back into the compute tile.

 

[OneEng2]

Keep in mind the vast majority of Intel's client sales in 2025 will be Raptor and Bartlett. Probally 2026 too.

How do you figure? Not saying you aren't correct, just wondering how you see that being the case.

Lunar Lake is mostly monolithic with a small IO die.
Arrow Lake has more tiles, so only CPU Tile is on the most advanced node, other tiles are on less expensive nodes.
But both have an overhead of more expensive packaging.

In mainstream market next year, it will be ~170 mm2 Kraken on N4P.
Lunar Lake at ~170 mm2 N3B + IO die + packaging

So Lunar Lake will be priced out of mainstream marked due to high cost. It will be only a premium MacBook Air competitor. Intel could, in theory, try to increase the size of this market by persuading customers it is worthwhile to spend extra ~ $300 on their laptop. We will see how it plays out.

It doesn't make sense, on the surface, that the same LNL core on N4P would be the same die size as it is on N3B. Can you explain?

Which one is 140 mm2, Kraken or LNL?

Edit: Looks like Lunar Lake is:
Compute die: 140 mm2
IO die: 46 mm2

What I had seen is that the current LNL is 170 mm2 on N3B plus the IO die @ 46 mm2 plus some glue chip that looks to be about 20 mm2.

AMD's Strix Point has a much bigger monolithic die size of 233 mm2, but also has a much less complex packaging. Also, Strix Point has 12 cores (with SMT) vs the 8 of LNL without.

To me, LNL using Intel's shiny new architecture on the best TSMC process node possible is still going to have its hands full with AMD's Zen 5 lineup in the laptop market in general, but LNL does look like a pretty promising CPU for thin and light.

This whole "get rid of SMT" thing might work OK in a laptop, but I am wondering how this is going to play out in the high end data center. AMD's SMT gains them about 25% per core in threaded application execution. I suspect that having SMT in Zen 5c in a 192 core configuration in Turin AND having a more efficient process node @ N3E (vs N4P), Skymont cores might not feel so efficient in comparison any more..... but I could be wrong. I am just curious as to how this whole "no SMT" thing is going to work out for Intel.

 

[poke01]

This strange obsession with ARM IPC is beyond me, there are two approaches to Core performance. You can go wide with less stages and lower clockspeed and get high performance or go less wide more stages and high clockspeed for high performance. Each approach has its pros and cons. X86 has the IO, expandability and software support advantage and as someone that does stuff with their system, this is the most important to me.

Wake me up when Apple has a Mac with an actual GPU or a PCIe slot and support for expansions cards. The Ampere workstation is a joke compared to Threadripper or Xeon as well.

This strange obsession with ARM IPC is beyond me, there are two approaches to Core performance. You can go wide with less stages and lower clockspeed and get high performance or go less wide more stages and high clockspeed for high performance. Each approach has its pros and cons. X86 has the IO, expandability and software support advantage and as someone that does stuff with their system, this is the most important to me.

Wake me up when Apple has a Mac with an actual GPU or a PCIe slot and support for expansions cards. The Ampere workstation is a joke compared to Threadripper or Xeon as well.

When we talk about ARM, it’s for laptops. I don’t ever see ARM becoming viable for desktops.

This whole thread is Arrow lake/Lunar lake, Meteor lake and Panther lake.

Lunar, Meteor and Panther are mobile only releases, of course the ARM laptop discussion would come up.

 

[dttprofessor]

How do you figure? Not saying you aren't correct, just wondering how you see that being the case.

It doesn't make sense, on the surface, that the same LNL core on N4P would be the same die size as it is on N3B. Can you explain?

What I had seen is that the current LNL is 170 mm2 on N3B plus the IO die @ 46 mm2 plus some glue chip that looks to be about 20 mm2.

AMD's Strix Point has a much bigger monolithic die size of 233 mm2, but also has a much less complex packaging. Also, Strix Point has 12 cores (with SMT) vs the 8 of LNL without.

To me, LNL using Intel's shiny new architecture on the best TSMC process node possible is still going to have its hands full with AMD's Zen 5 lineup in the laptop market in general, but LNL does look like a pretty promising CPU for thin and light.

This whole "get rid of SMT" thing might work OK in a laptop, but I am wondering how this is going to play out in the high end data center. AMD's SMT gains them about 25% per core in threaded application execution. I suspect that having SMT in Zen 5c in a 192 core configuration in Turin AND having a more efficient process node @ N3E (vs N4P), Skymont cores might not feel so efficient in comparison any more..... but I could be wrong. I am just curious as to how this whole "no SMT" thing is going to work out for Intel.

Lunar lake cpu tile <140 mm2

 

[Doug S]

When we talk about ARM, it’s for laptops. I don’t ever see ARM becoming viable for desktops.

Why?

It isn't like an M4 Max wouldn't make for a killer desktop. The problem is, desktops are a shrinking market, increasingly pigeonholed between gamers and people who use them in traditional "workstation" roles (i.e. what people used to buy RISC workstations for back in the day) so stuff like expandability to add a GPU (i.e. @AcrosTinus's bias apparently only considering something with PCIe slots as a "real PC") for those fewer and fewer customers shopping desktops.

There's nothing inherent about ARM that makes it a problem to support PCIe or third party GPUs. It just isn't a worth seriously pursuing when gamers are locked in to x86 for legacy reasons and workstation users are looking for essentially server CPUs in desktop clothing - and Apple and Qualcomm do not have server CPUs to offer them. If Apple added a PCIe slot to their entire desktop line including the Mini and announced they will provide full support for third party GPUs does anyone really believe Nvidia or AMD would bother porting their GPU driver? There wouldn't be enough sales, because for most customers Apple's GPU is more than good enough and for those who want more they would also need either a huge number of games to be ported or for Apple to build some frankenchip with 8 Maxes tied together to compete with the biggest dual socket Epyc/Xeon offerings on MT (oh and for much more RAM to be supported too)

 

[Joe NYC]

What I had seen is that the current LNL is 170 mm2 on N3B plus the IO die @ 46 mm2 plus some glue chip that looks to be about 20 mm2.

There is no official number on die size on Lunar Lake from Intel, only some extimates on Twitter of 140mm2 N3 + 46mm2 N6. The third thing in the corner that looks like another die is just a filler.

AMD's Strix Point has a much bigger monolithic die size of 233 mm2, but also has a much less complex packaging. Also, Strix Point has 12 cores (with SMT) vs the 8 of LNL without.

Lunar Lake cost is probably close to 12 core Strix Point, but they are addressing different market.

I went on line and found most of the Laptops with Strix Point in the highest end gaming laptops, most including NVidia GPU (in $2,000+ range), very few on the market without dGPU, in Lunar Lake price range. One possibility is that most of the iGPU only Strix Point were sold out.

It's still just days from Lunar Lake launch and the new models are still trickling in.

To me, LNL using Intel's shiny new architecture on the best TSMC process node possible is still going to have its hands full with AMD's Zen 5 lineup in the laptop market in general, but LNL does look like a pretty promising CPU for thin and light.

Yeah, different segments between Strix Point, Lunar Lake and upcoming Kraken.

Strix Point - high end and gaming
Lunar Lake - premium thin and linght
Kraken - mainstream pricing segment, with CoPilot branding (if anyone cares)

This whole "get rid of SMT" thing might work OK in a laptop, but I am wondering how this is going to play out in the high end data center. AMD's SMT gains them about 25% per core in threaded application execution. I suspect that having SMT in Zen 5c in a 192 core configuration in Turin AND having a more efficient process node @ N3E (vs N4P), Skymont cores might not feel so efficient in comparison any more..... but I could be wrong. I am just curious as to how this whole "no SMT" thing is going to work out for Intel.

I think for Lunar Lake, no SMT is no problem. It was probably a good decision by Intel for target market of Lunar Lake, if it, even marginally contributed to better ST, smaller die, better efficiency.

I don't think Sierra Forrest will be very competitive vs. Turin Dense either with SMT on or off (on Turin), but Clearwater Forrest with Skymont cores may be a different story. Likely clearly superior vs. Turin Dense with SMT off.

 

[511]

I don't think Sierra Forrest will be very competitive vs. Turin Dense either with SMT on or off (on Turin), but Clearwater Forrest with Skymont cores may be a different story. Likely clearly superior vs. Turin Dense with SMT off.

The 288 Core variants can or can not be competitive on some targeted workloads but CLWF will certainly be better than 192C/384T in non AVX-512 Workloads 288 Physical cores vs 192C/384T and they are Chadmont not weak like Sierra Forest

 

[alcoholbob]

There is no official number on die size on Lunar Lake from Intel, only some extimates on Twitter of 140mm2 N3 + 46mm2 N6. The third thing in the corner that looks like another die is just a filler.



Lunar Lake cost is probably close to 12 core Strix Point, but they are addressing different market.

I went on line and found most of the Laptops with Strix Point in the highest end gaming laptops, most including NVidia GPU (in $2,000+ range), very few on the market without dGPU, in Lunar Lake price range. One possibility is that most of the iGPU only Strix Point were sold out.

It's still just days from Lunar Lake launch and the new models are still trickling in.



Yeah, different segments between Strix Point, Lunar Lake and upcoming Kraken.

Strix Point - high end and gaming
Lunar Lake - premium thin and linght
Kraken - mainstream pricing segment, with CoPilot branding (if anyone cares)



I think for Lunar Lake, no SMT is no problem. It was probably a good decision by Intel for target market of Lunar Lake, if it, even marginally contributed to better ST, smaller die, better efficiency.

I don't think Sierra Forrest will be very competitive vs. Turin Dense either with SMT on or off (on Turin), but Clearwater Forrest with Skymont cores may be a different story. Likely clearly superior vs. Turin Dense with SMT off.

Arrow Lake supposedly will have hyperthreading, it's just "optional" and likely will be enabled for server parts.

That said hyperthreading is "free" performance", but the majority of the gains comes at the cost of more power consumption. If you are in a power constrained system, HT gains are much slimmer, closer to 6-10% more multi-core performance per watt, at the cost of 2-3% single threaded performance. Once you have enough threads to cover any conceivable workload, you are better off focusing back on more ST performance IMO.

 

[511]

Fun Fact Lion Cove won't be in servers it will be Panther Cove

 

[igor_kavinski]

Arrow Lake supposedly will have hyperthreading

It would've been nice to have it anyways since the expanded core structures in Lion Cove would've helped boost HT performance better.

Sigh.

First it was AVX-512. Now it's HT.

Intel, you keep finding ways to disappoint people.

Heck, even Skymont should've had HT. Let people use it if it accelerates their workloads and keep it off by default in laptops or pre-builts.

I would hazard a guess that they tried HT in the early samples but it made the power consumption go beyond 270W so they ditched it.

 

[511]

Skymont never had HT so no point my biggest issue has Been been Optional AVX-512 why just let people run 8 core AVX-513 even if they buy 8+16

 

[igor_kavinski]

Skymont never had HT

Wouldn't have been a real challenge for them since AMD managed it with Zen 4c/5c. Funny that Intel's "world class" engineering teams can't figure out how to do both AVX-512 and HT in their e-cores while AMD is lying comfortably in a hammock, looking at their struggles and chuckling to themselves, "Amateurs!".

Changes in Intel's Technology, Systems Architecture and Client Group...

Intel announces that Jim Keller has resigned due to personal reasons.

www.intel.com

Intel congratulates Sundari, Gloria, Gene, Uri, Boyd, Daaman and Navid as we begin the next phase of our world-class engineering organization and look forward to executing on our exciting roadmap of products.

 

[poke01]

Wouldn't have been a real challenge for them since AMD managed it with Zen 4c/5c. Funny that Intel's "world class" engineering teams can't figure out how to do both AVX-512 and HT in their e-cores while AMD is lying comfortably in a hammock, looking at their struggles and chuckling to themselves, "Amateurs!".

Idk, Skymont is truly impressive and chipsandcheese agree as well. Maybe take your baseless jokes elsewhere.

 

[FlameTail]

Wouldn't have been a real challenge for them since AMD managed it with Zen 4c/5c. Funny that Intel's "world class" engineering teams can't figure out how to do both AVX-512 and HT in their e-cores while AMD is lying comfortably in a hammock, looking at their struggles and chuckling to themselves

I don't see why the lack of HT is a problem for Intel's E-cores, but yes the lack of AVX-512 is.

Perhaps 512b AVX will come to Nova Lake's E-cores.

According to a user on the real world technologies forum, Panther Cove will represent a big architectural overhaul of Intel's P-core design, featuring "large IPC" improvements as well as support for Intel's APX and AVX10 standards

Panther Cove will reportedly arrive with big IPC improvements, support for Intel APX

Panther Cove is one of the furthest out P-core CPU architectures being designed by Intel

www.tomshardware.com

 

[igor_kavinski]

Idk, Skymont is truly impressive

Could've been at least 20% more impressive with HT in MT workloads. Then add at least 10% on top of that for workloads that can leverage both HT and AVX-512. It's sad to see this 800 pound gorilla languishing the way they have been for the past few years. Perhaps Nova Lake will fix things?

 

[511]

IMO what they should do with Nova Lake Add full fledged AVX-512 for P cores which they already have and add double Pumped AVX-512 like Zen 4 in E cores perfect solution

 

[igor_kavinski]

I don't see why the lack of HT is a problem for Intel's E-cores

It's "free" performance, as in up to 25% more MT perf with just 5% extra transistors per core.

 

[Kepler_L2]

Perhaps 512b AVX will come to Nova Lake's E-cores.

The whole point of AVX10 is you don't need to do 512b vectors.

 

[coercitiv]

It's "free" performance, as in up to 25% more MT perf with just 5% extra transistors per core.

It's not free, and it also needs synergy with the rest of the design. Intel chose to go a different path with E cores, and as long as they're willing to keep a high number of E cores in the mainstream consumer platform... HT is optional for them.

The transistor cost is ~10% or higher based on what we know from other companies and also based on napkin math using Intel's own marketing slides:

So according to Intel, performance improves by ~30% when using SMT. At the same time removing SMT logic results in only a 15% perf/area loss, so the SMT core has about 17.5% better perf/area. This means the SMT enabled core is ~10.5% larger.

For the sake of napkin math, let's assume HT uses 12.5% more core area. In a design with 8P cores, the savings would accumulate to 100% of a P core, or roughly 3 E cores (the modern ones). Modern E cores to P core equivalence is probably something 3:2 (based on very rough math I just did in my head), so the savings from removing HT can be used to increase MT performance by about 25%. And that with less threads, so arguably better scaling. Everybody can chill now, nothing was lost.

There's a catch though, the design needs to be hybrid and this brings a host of other tradeoffs and design decisions. The loss of HT is arguably the least of Intel's worries. As long as consumer Lion Cove does not spend the transistor budget to include HT and keep it disabled in firmware, everything is just fine and the saving can translate to either more E cores or lower price. (or an NPU, so we can all weep silently in a corner).

 

[igor_kavinski]

As long as consumer Lion Cove does not spend the transistor budget to include HT and keep it disabled in firmware, everything is just fine and the saving can translate to either more E cores or lower price.

That's the doubtful part. What if Lion Cove core has transistors for both AVX-512 and HT but Intel chose to disable them because reasons? If that really is the case, no cost savings for Intel to pass them onto consumers, no extra cores from the transistor budget savings and loss of potential FP and MT performance for end users. Lose-lose situation mainly for consumers.

Those Intel slides trying to excuse the lack of SMT were made precisely to avoid the negative PR of losing a feature they once touted so much.