Discussion Intel Meteor, Arrow, Lunar & Panther Lakes + WCL Discussion Threads

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Tigerick

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Wildcat Lake (WCL) Preliminary Specs

Intel Wildcat Lake (WCL) is upcoming mobile SoC replacing ADL-N. WCL consists of 2 tiles: compute tile and PCD tile. It is true single die consists of CPU, GPU and NPU that is fabbed by 18-A process. Last time I checked, PCD tile is fabbed by TSMC N6 process. They are connected through UCIe, not D2D; a first from Intel. Expecting launching in Q2/Computex 2026. In case people don't remember AlderLake-N, I have created a table below to compare the detail specs of ADL-N and WCL. Just for fun, I am throwing LNL and upcoming Mediatek D9500 SoC.

Intel Alder Lake - NIntel Wildcat LakeIntel Lunar LakeMediatek D9500
Launch DateQ1-2023Q2-2026 ?Q3-2024Q3-2025
ModelIntel N300?Core Ultra 7 268VDimensity 9500 5G
Dies2221
NodeIntel 7 + ?Intel 18-A + TSMC N6TSMC N3B + N6TSMC N3P
CPU8 E-cores2 P-core + 4 LP E-cores4 P-core + 4 LP E-coresC1 1+3+4
Threads8688
Max Clock3.8 GHz?5 GHz
L3 Cache6 MB?12 MB
TDP7 WFanless ?17 WFanless
Memory64-bit LPDDR5-480064-bit LPDDR5-6800 ?128-bit LPDDR5X-853364-bit LPDDR5X-10667
Size16 GB?32 GB24 GB ?
Bandwidth~ 55 GB/s136 GB/s85.6 GB/s
GPUUHD GraphicsArc 140VG1 Ultra
EU / Xe32 EU2 Xe8 Xe12
Max Clock1.25 GHz2 GHz
NPUNA18 TOPS48 TOPS100 TOPS ?






PPT1.jpg
PPT2.jpg
PPT3.jpg



As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.



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Det0x

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ISkymont is legitimately the most exciting x86 core since at least Zen 1
That kinda depends on what perspective your looking from i guess, being a "overclocker" myself i would much rather have a core that actually showed good scaling all the way up to lets say ~25w

Oh well, each to their own.. That's a good x86 result for sub 1w to ~1.5w for whatever it's worth 👍
btw, i take it this is also the sub 1w range where we are getting this +60% performance increase for the e-core ?
 
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Gideon

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Plenty of 285K runs


Seem comparable to 9950X's scores
Wait, wasn't this thread full of people claiming, it will easily outperform a 9950X couple of months ago?

Claiming that the new E-cores will smoke it in anything MT and because "Arrow Lake versions of Lion Cove will be much better than Lunar Lake"?

In Geekbench at least they appear to be about the same.
 

Josh128

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Wait, wasn't this thread full of people claiming, it will easily outperform a 9950X couple of months ago?

Claiming that the new E-cores will smoke it in anything MT and because "Arrow Lake versions of Lion Cove will be much better than Lunar Lake"?

In Geekbench at least they appear to be about the same.
It looks like all these latest runs are all sandbagging with 5600MT/s RAM. Instead of letting the cat out of the bag literally weeks ahead of time like AMD did with Zen 5, Intel is doing the proper thing and leaving some room for positive surprise at launch. With the CUDIMM RAM supposedly hitting over 9000MT/s, its going to score significantly higher than this. We've already seen 3450/23K+ runs, I think its going to be ~3500/24K+ come launch time.
 

Magio

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That kinda depends on what perspective your looking from i guess, being a "overclocker" myself i would much rather have a core that actually showed good scaling all the way up to lets say ~25w

But the thing is x86 is already pretty good at that. Skymont however is as far as I can remembe unprecedented for true low power performance if this graph is to be believed.

It would obviously have to broaden its range of operation quite a lot to become a viable "unified" core, but it already provides something unique which on mobile platforms is a true ace in the hole.
 

coercitiv

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I don't know if this was posted but if accurate, Skymont is legitimately the most exciting x86 core since at least Zen 1. Scales to lower power than any x86 core before it while delivering higher sub-1W performance than any x86 core ever has by a long shot.
The efficiency results in Huang's blog are very interesting but limited by his options to collect the data at this time, probably limited time to analyze as well. For example, here's his results for nT (4 cores):
1727791090697.png

Even if we ignore the 4C8T numbers, the 4C4T numbers for Zen5C look much better than in the isolated 1C results. At the same time the Lion Cove data points are probably incorrect, or at least I hope they are.
 

OneEng2

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They are axing P-core. E-core offers way more potential. Skymont ain't designed to top performance but good area efficiency, yet they are still heels on P-core. So future is build on E-core, with clustered decode and without mop cache.
I think that in the laptop and desktop markets where the cost of goods is vitally important for profits, space efficiency is going to start being a big consideration.

I have always felt that Intel maintained it's superiority in performance by always having the better process to put its designs on.

It will be very interesting to see how the money shakes out between AMD and Intel now that Intel's CPU designers must now be much more space conscious lest they create a very competitive CPU that can't make a profit when sold.
 
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MarkPost

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It looks like all these latest runs are all sandbagging with 5600MT/s RAM. Instead of letting the cat out of the bag literally weeks ahead of time like AMD did with Zen 5, Intel is doing the proper thing and leaving some room for positive surprise at launch. With the CUDIMM RAM supposedly hitting over 9000MT/s, its going to score significantly higher than this. We've already seen 3450/23K+ runs, I think its going to be ~3500/24K+ come launch time.
5600MT/s RAM seems to be the official memory supported. Anyways as I said here https://forums.anandtech.com/thread...akes-discussion-threads.2606448/post-41307554 there are entries with 6400 and 7200 too
 
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9949asd

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ikjadoon

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Those are the 4-slot speeds, which are (likely) a little lower than ARL-S' max JEDEC speeds. From 50 (!) pages ago:

Alder LakeRaptor LakeArrow Lake
2-slot: 1DPC 1R48005600? [6400?]
2-slot: 1DPC 2R48005200? [6000?]
4-slot: 1DPC 1R440048005600
4-slot: 1DPC 2R440044005600
4-slot: 2DPC 1R400040004800
4-slot: 2DPC 2R360036004400
CAMM2N/AN/A??

That is, Intel's "up to" DRAM speeds are 2-slot 1DPC 1R. We need a leak of a 2-slot motherboard's JEDEC speeds. Of course, most people running these motherboards won't use JEDEC, but OEM motherboards (most with 2 slots for cost-saving) are probably faster than JEDEC 5600.

The terms, if helpful:
2-slot: motherboard with 2x DIMM slots
4-slot: motherboard with 4x DIMM slots
1DPC: 1x DIMM per channel
2DPC: 2x DIMMs per channel
1R: single-rank
2R: dual-rank


EDIT: see this updated comment with better data from @Cstops: https://forums.anandtech.com/thread...akes-discussion-threads.2606448/post-41309075
 
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MarkPost

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Those are the 4-slot speeds, which are (likely) a little lower than ARL-S' max JEDEC speeds. From 50 (!) pages ago:

Alder LakeRaptor LakeArrow Lake
2-slot: 1DPC 1R48005600? [6400?]
2-slot: 1DPC 2R48005200? [6000?]
4-slot: 1DPC 1R440048005600
4-slot: 1DPC 2R440044005600
4-slot: 2DPC 1R400040004800
4-slot: 2DPC 2R360036004400
CAMM2N/AN/A??

That is, Intel's "up to" DRAM speeds are 2-slot 1DPC 1R. We need a leak of a 2-slot motherboard's JEDEC speeds. Of course, most people running these motherboards won't use JEDEC, but OEM motherboards (most with 2 slots for cost-saving) are probably faster than JEDEC 5600.

The terms, if helpful:
2-slot: motherboard with 2x DIMM slots
4-slot: motherboard with 4x DIMM slots
1DPC: 1x DIMM per channel
2DPC: 2x DIMMs per channel
1R: single-rank
2R: dual-rank
I dont understand your argument. For example, two ASUS Z790 boards (one with 2 dimms, the other with 4 dimms):

two dimms: 2 x DIMM slots, Max. 96GB, DDR5 8200+(OC)/8000(OC)/7800(OC)/7600(OC)/7400(OC)/7200(OC)/7000(OC)/6800(OC)/6600(OC)/6400(OC)/6200(OC)/6000(OC)/5800(OC)/5600/5400/5200/5000/4800

four dimms: https://www.asus.com/motherboards-components/motherboards/others/z790-gaming-wifi7/techspec/
4 x DIMM slots, Max. 192GB, DDR5 7200 (OC)/7000(OC)/6800(OC)/6600(OC)/6400(OC)/ 6200(OC)/ 6000(OC)/ 5800(OC)/ 5600/ 5400/ 5200/ 5000/ 4800

So the official memory support for both boards is up to 5600. Above that is OC
 

Cstops

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I dont understand your argument. For example, two ASUS Z790 boards (one with 2 dimms, the other with 4 dimms):

two dimms: 2 x DIMM slots, Max. 96GB, DDR5 8200+(OC)/8000(OC)/7800(OC)/7600(OC)/7400(OC)/7200(OC)/7000(OC)/6800(OC)/6600(OC)/6400(OC)/6200(OC)/6000(OC)/5800(OC)/5600/5400/5200/5000/4800

four dimms: https://www.asus.com/motherboards-components/motherboards/others/z790-gaming-wifi7/techspec/
4 x DIMM slots, Max. 192GB, DDR5 7200 (OC)/7000(OC)/6800(OC)/6600(OC)/6400(OC)/ 6200(OC)/ 6000(OC)/ 5800(OC)/ 5600/ 5400/ 5200/ 5000/ 4800

So the official memory support for both boards is up to 5600. Above that is OC
I’m probably misreading it this above altogether here but specifically on max ‘officially supported’ memory speeds for Intel, it’s dependent on both whether the board is configured for 1dpc (e.g. 1 slot per memory channel) or two dpc (2 slots per memory channel) then whether it’s single or dual rank.

P. 112–113 (Table 25) of Intel’s data sheet comes to mind here (plus the notes for said table, particular note 1 on how dpc is being defined) if that helps for context.

13th Generation Intel® CoreTM and Intel® CoreTM 14th Generation Processors Datasheet, Volume 1 of 2
 
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ikjadoon

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I dont understand your argument. For example, two ASUS Z790 boards (one with 2 dimms, the other with 4 dimms):

So the official memory support for both boards is up to 5600. Above that is OC

Interesting; I used ASRock as the leak was ASRock:

ASRock Z790:
Max. 5600 JEDEC on 2-slot motherboards (A, B, C)
Max. 5200 JEDEC on 4-slot motherboards (A, B, C, D, E)

From a spot check: Gigabyte has lower JEDEC speeds on 4-slot motherboards, but MSI & ASUS both advertise 5600 JEDEC on 4-slot motherboards.
 

DavidC1

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Even if we ignore the 4C8T numbers, the 4C4T numbers for Zen5C look much better than in the isolated 1C results. At the same time the Lion Cove data points are probably incorrect, or at least I hope they are.
This could also be that Intel deliberately chose to optimize for 1T results versus MT, knowing full well that 4+4 wouldn't be a class leader anyway even if it did well, and battery life in MT is primarily determined by TDP and ignores virtually most of the power saving improvements.

You can also see that package level wise, Crestmont LP is seriously behind Crestmont in efficiency, while at the core level they are the same.
 

ikjadoon

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I’m probably misreading it this above altogether here but specifically on max ‘officially supported’ memory speeds for Intel, it’s dependent on both whether the board is configured for 1dpc (e.g. 1 slot per memory channel) or two dpc (2 slots per memory channel) then whether it’s single or dual rank.

P. 112–113 (Table 25) of Intel’s data sheet comes to mind here (plus the notes for said table, particular note 1 on how dpc is being defined) if that helps for context.

13th Generation Intel® CoreTM and Intel® CoreTM 14th Generation Processors Datasheet, Volume 1 of 2

Ah, thank you for this PDF. That clarifies it, particularly footnote 1:

1DPC refer to system with one DIMM slot routed per 64-bit channel, 2DPC refer to system with two DIMM slots routed per 64-bit channel.

I accidentally used 14th gen data (as I used the Z790 as reference), but your PDF makes it clearer between 13th vs 14th. The "1DPC" nomenclature also confused me earlier: it's 1x DIMM slot per channel, not 1x DIMM per channel.

Alder LakeRaptor LakeRaptor Lake RefreshArrow Lake
2-slot: 2xDIMM 1R480056005600? [6400?]
2-slot: 2xDIMM 2R480052005600? [6000?]
4-slot: 2xDIMM 1R4400440044005600
4-slot: 2xDIMM 2R4400440044005600
4-slot: 4xDIMM 1R4000400040004800
4-slot: 4xDIMM 2R3600360036004400
CAMM2N/AN/AN/A??

I imagine ASUS & MSI, then, are being a little generous with their claimed JEDEC max (which is fine).
 

gdansk

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Big If true
Semianalysis said:
The real high-volume introduction of GAA will be 2025 for all three large foundries, with Rapidus following in 2027. Intel will be first by a year or so with BSPDN, but at a density closer to 3 nm processes despite the name 18A.
Hmm? I thought it was more dense.
 

coercitiv

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This could also be that Intel deliberately chose to optimize for 1T results versus MT, knowing full well that 4+4 wouldn't be a class leader anyway even if it did well, and battery life in MT is primarily determined by TDP and ignores virtually most of the power saving improvements.
Intel clearly targeted lightly threaded scenarios for this chip, and we know for a fact the chip is very efficient in light loads. However, when discussing these early findings in Huang's blog, it's important to process them as early tests and not draw conclusions based exclusively on them.

For example, here's what he says about the 1T energy efficiency graph using Intel IA / AMD VDDCR (auto translation):
Skymont LPE outperforms all other cores across the entire power range it covers, with the IA power consumption reading at 2 GHz being only 0.05W.
Considering that Intel has used uncore FIVR to power the L2 cache of small cores in the past, we are currently unable to confirm how much of the small core range the Lunar Lake RAPL IA power consumption readings cover and how comparable they are with other cores, so this set of data is for reference only.

One could easily think that the 0.05W figure is just a typo... yet there it is represented in the graph as Skymont presumably offers at "near zero watts" the same perf that Crestmont gets at 1W+. Something is off here, and I want to make it clear I don't blame the author for these anomalies, as I'm well aware that what they attempted is probably impossible to with precision without access to more accurate data from the hardware.
1727851514103.png
 

AMDK11

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