Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

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Tigerick

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PPT1.jpg
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PPT3.jpg



As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.



Comparison of upcoming Intel's U-series CPU: Core Ultra 100U, Lunar Lake and Panther Lake

ModelCode-NameDateTDPNodeTilesMain TileCPULP E-CoreLLCGPUXe-cores
Core Ultra 100UMeteor LakeQ4 202315 - 57 WIntel 4 + N5 + N64tCPU2P + 8E212 MBIntel Graphics4
?Lunar LakeQ4 202417 - 30 WN3B + N62CPU + GPU & IMC4P + 4E012 MBArc8
?Panther LakeQ1 2026 ??Intel 18A + N3E3CPU + MC4P + 8E4?Arc12



Comparison of die size of Each Tile of Meteor Lake, Arrow Lake, Lunar Lake and Panther Lake

Meteor LakeArrow Lake (20A)Arrow Lake (N3B)Lunar LakePanther Lake
PlatformMobile H/U OnlyDesktop OnlyDesktop & Mobile H&HXMobile U OnlyMobile H
Process NodeIntel 4Intel 20ATSMC N3BTSMC N3BIntel 18A
DateQ4 2023Q1 2025 ?Desktop-Q4-2024
H&HX-Q1-2025
Q4 2024Q1 2026 ?
Full Die6P + 8P6P + 8E ?8P + 16E4P + 4E4P + 8E
LLC24 MB24 MB ?36 MB ?12 MB?
tCPU66.48
tGPU44.45
SoC96.77
IOE44.45
Total252.15

LNL-MX.png

Intel Core Ultra 100 - Meteor Lake

INTEL-CORE-100-ULTRA-METEOR-LAKE-OFFCIAL-SLIDE-2.jpg

As mentioned by Tomshardware, TSMC will manufacture the I/O, SoC, and GPU tiles. That means Intel will manufacture only the CPU and Foveros tiles. (Notably, Intel calls the I/O tile an 'I/O Expander,' hence the IOE moniker.)



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poke01

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Hmm interesting people have low expectations. Remember this is a ST score. Obviously for MT it will go over 30 watts.


This is an engineering sku too. I guess I might be wrong then.
 

ikjadoon

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Sep 4, 2006
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5 GHz at 15W is def. possible; it depends on the uArch and how power is measured (uncore? idle-normalized? AC vs DC?)

7840U @ 5.1 GHz peak claimed boost
21W - 23W peaks on GB6
As measured by Phoronix

That was N4. So N3B should help some, no? And we'll see how much / little Lion Cove demands in power. Still hoping for some fanless models. It'd certainly be ironic if LNL had more fanless design wins than Oryon (0 designs).
 
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DavidC1

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Hmm interesting people have low expectations. Remember this is a ST score. Obviously for MT it will go over 30 watts.

This is an engineering sku too. I guess I might be wrong then.
It's possible. The x86 chips have high uncore/idle power so if they got that lowered in Lunarlake, the peak power will go down by the same amount. So node advancements plus minus ~2-3W. On current chips the E core ST efficiency is made worse by the high idle consumption. So the 8W E core ST could be actually 5W.

Considering the ARM competition does it at less than 1/2 the power, it isn't anything fantastic either.
Still hoping for some fanless models. It'd certainly be ironic if LNL had more fanless design wins than Oryon (0 designs).
I'm very disappointed the state of the art efficient battery life designs are all hobbled by 2K resolution OLED displays.

Where is the IPS 1080p ultraportables? If it's actually that efficient it doesn't need a honking 75WHr battery. 50WHr would be more than enough.

Look at this device from 4 years ago: https://www.notebookcheck.net/Acer-...ent-long-lasting-14-inch-laptop.586141.0.html

29 hour idle, 11hr WiFi surfing, 16 hour video playback all on a 50WHr battery. "Efficient" Lunarlake devices still can't catch up to that despite having 70WHr+ batteries, at least not the models we know.

You would think Lunarlake would be able to beat the above device using just a 40WHr battery.
 
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Magio

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I'm very disappointed the state of the art efficient battery life designs are all hobbled by 2K resolution OLED displays.

Where is the IPS 1080p ultraportables? If it's actually that efficient it doesn't need a honking 75WHr battery. 50WHr would be more than enough.

I think you'll see more of that in the second round of LNL designs whenever those drop. This first salvo at IFA was really centered on the super premium segment which kind of demands great screens so that's what most of these are equipped with.

LNL is not gonna be in entry level designs any time soon if ever but it will find its way in the upper midrange over the next several months and those will be more likely to ship with lower res IPS panels.
 
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Magio

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Has anyone seen a Linux result for LNL on Geekbench? I searched for a few SKUs but didn't find anything. Linux usually has a small but noticeable lead on Windows so I'm intrigued to see how LNL fares on there.
 

Magio

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N3B as a 3nm process is indeed a full node advancement over N4P (which really is a 5nm variant), however N3B in particular was a particularly embattled process which forced TSMC to scale back on its density ambitions and other aspects. Still a noticeable improvement over N4P but far inferior to what's expected of N3E for example.

It's a bit ironic that the first time Intel properly bet on TSMC was on the one node from them that didn't turn out to be a really great one.
 
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jpiniero

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N3B as a 3nm process is indeed a full node advancement over N4P (which really is a 5nm variant),

Not really. The only thing it's decently better on is logic density... but the price increase makes it moot. Apple discontinued the iPhone 15 Pro so Lunar and Arrow will be the only products on the market using N3B.
 

511

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Jul 12, 2024
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N3B as a 3nm process is indeed a full node advancement over N4P (which really is a 5nm variant), however N3B in particular was a particularly embattled process which forced TSMC to scale back on its density ambitions and other aspects. Still a noticeable improvement over N4P but far inferior to what's expected of N3E for example.

It's a bit ironic that the first time Intel properly bet on TSMC was on the one node from them that didn't turn out to be a really great one.
Yeah it strikes me comical intel will pray that tsmc gets delayed for them to take lead back🤣
 
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Magio

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Not really. The only thing it's decently better on is logic density... but the price increase makes it moot. Apple discontinued the iPhone 15 Pro so Lunar and Arrow will be the only products on the market using N3B.
Logic density also helps power consumption. In the case of N3B, poor yields among other things meant it didn't improve performance as much as a full node jump usually would but PPW would inherently see improvements (which we saw from M2 to M3).

And there will be M3 Macs on sale for the foreseeable future.

Yeah it strikes me comical intel will pray that tsmc gets delayed for them to take lead back🤣

Of course Intel wouldn't mind seeing TSMC suffer delays on N2, but really they don't need TSMC delays to look good. If they execute 18A well and on schedule (which would see it ramp to HVM before N2 does) that would be a huge win even if N2 still snatches the "best process in the world" crown back shortly after. (And of course Intel will focus on its process' strengths to argue process leadership while conveniently ignoring the areas in which TSMC will likely be better.)
 

SiliconFly

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So so better power efficiency? Source?
Source for what?

That’s a nice frequency bump for MTL Intel 3. Intel 3 looks to be maturing.
Intel 3 is turning out to be better than expected. We'll have better insights once GNR & SRF come out.

... Of course Intel wouldn't mind seeing TSMC suffer delays on N2, but really they don't need TSMC delays to look good. If they execute 18A well and on schedule (which would see it ramp to HVM before N2 does) that would be a huge win even if N2 still snatches the "best process in the world" crown back shortly after. (And of course Intel will focus on its process' strengths to argue process leadership while conveniently ignoring the areas in which TSMC will likely be better.)
Intel *needs* TSMC to stay ahead of competition. TSMC delays (if any) will impact Intel negatively.
 

Magio

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Intel *needs* TSMC to stay ahead of competition. TSMC delays (if any) will impact Intel negatively.

It would impact (some) of their products negatively but it would help them get their foundries back to leadership which is a much more impactful thing. If TSMC suffers delays, it hurts *all* of Intel's competitors and only some of Intel's products, while if Intel's foundries take the lead as a result it would help them nail some very lucrative contracts with top chipmakers.
 

SiliconFly

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It would impact (some) of their products negatively but it would help them get their foundries back to leadership which is a much more impactful thing. If TSMC suffers delays, it hurts *all* of Intel's competitors and only some of Intel's products, while if Intel's foundries take the lead as a result it would help them nail some very lucrative contracts with top chipmakers.
True
 

511

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It would impact (some) of their products negatively but it would help them get their foundries back to leadership which is a much more impactful thing. If TSMC suffers delays, it hurts *all* of Intel's competitors and only some of Intel's products, while if Intel's foundries take the lead as a result it would help them nail some very lucrative contracts with top chipmakers.
This 100% TSMC is Successful due to Intel delays + their execution
 

Hitman928

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So so better power efficiency? Source?
1726500106712-png.107663


Logic density also helps power consumption.

How so?

In the case of N3B, poor yields among other things meant it didn't improve performance as much as a full node jump usually would but PPW would inherently see improvements (which we saw from M2 to M3).

I haven't heard that N3B has particularly poor yields after the delay. Maybe a little worse than TSMC's other nodes, but still good for production. It is a more expensive node though. The PPW advantage over N4P is pretty small.

Of course Intel wouldn't mind seeing TSMC suffer delays on N2, but really they don't need TSMC delays to look good. If they execute 18A well and on schedule (which would see it ramp to HVM before N2 does) that would be a huge win even if N2 still snatches the "best process in the world" crown back shortly after. (And of course Intel will focus on its process' strengths to argue process leadership while conveniently ignoring the areas in which TSMC will likely be better.)

Early reports are that customers aren't overly enthusiastic about 18a, but it hasn't actually released yet so we'll see how well it does when it lands.