Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

[Tigerick]

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.



Comparison of upcoming Intel's U-series CPU: Core Ultra 100U, Lunar Lake and Panther Lake

Model	Code-Name	Date	TDP	Node	Tiles	Main Tile	CPU	LP E-Core	LLC	GPU	Xe-cores
Core Ultra 100U	Meteor Lake	Q4 2023	15 - 57 W	Intel 4 + N5 + N6	4	tCPU	2P + 8E	2	12 MB	Intel Graphics	4
?	Lunar Lake	Q4 2024	17 - 30 W	N3B + N6	2	CPU + GPU & IMC	4P + 4E	0	12 MB	Arc	8
?	Panther Lake	Q1 2026 ?	?	Intel 18A + N3E	3	CPU + MC	4P + 8E	4	?	Arc	12

Comparison of die size of Each Tile of Meteor Lake, Arrow Lake, Lunar Lake and Panther Lake

	Meteor Lake	Arrow Lake (N3B)	Lunar Lake	Panther Lake
Platform	Mobile H/U Only	Desktop & Mobile H&HX	Mobile U Only	Mobile H
Process Node	Intel 4	TSMC N3B	TSMC N3B	Intel 18A
Date	Q4 2023	Desktop-Q4-2024 H&HX-Q1-2025	Q4 2024	Q1 2026 ?
Full Die	6P + 8P	8P + 16E	4P + 4E	4P + 8E
LLC	24 MB	36 MB ?	12 MB	?
tCPU	66.48
tGPU	44.45
SoC	96.77
IOE	44.45
Total	252.15

Intel Core Ultra 100 - Meteor Lake



As mentioned by Tomshardware, TSMC will manufacture the I/O, SoC, and GPU tiles. That means Intel will manufacture only the CPU and Foveros tiles. (Notably, Intel calls the I/O tile an 'I/O Expander,' hence the IOE moniker.)

 

[BorisTheBlade82]

Ok. I'll try a different approach. Here's a link to an anandtech article about power/performance/density of TSMC nodes for reference.

When a foundry says their node has 20% increase in performance per watt over previous generation, or 40% power savings over previous generation (but not both at the same time), they're usually talking about industry averages while using logic circuits like cpu (not srams). In other words, the CPU gets upto 20% performance increase or upto 40% reduction in power (but not both) over the previous generation node for the same micro architecture (uArch).

Pls check the anandtech article above. Here's a link to another similar article by tomshardware. This article also talks about the node's "speed improvement", power savings & density.

The "speed improvement" or "performance increase" numbers advertised by the nodes like TSMC, Samsung, Intel is typically based on CPUs (logic). They calculate it based on power, frequency & density. For example, TSMC N3 will be upto 15% faster than N5 for the same power and given the same area (when they say same area, they're talking about increase in logic (like bigger L2/L3 caches) due to the additional logic in the die because of the increase in logic density). This was mentioned by TSMC CEO himself when questioned by journalists. And this measure (PPW, PPA or power/performance/density) has been spot on for the nodes for many years now. Even though it's a estimate based on averages, it's still the best measure for the nodes at the moment.

So, in essence, switching to an advanced node will automatically give us better performance for the same architecture at the same frequency due to the extra logic, extra L2/L3 caches, better interconnects, etc.

As @Exist50 already noted, you seem to be under a wrong impression. The performance figures provided by TSMC (and others as well) are derived from frequency scaling of a reference chip - mostly an ARM Axxx design.

Under no circumstances would TSMC speculate, what kind of architectural improvements their new process might enable for an AMD ZEN n+1 or an Apple M n+1 of their customers.

As a result you can not assume, that MTL will automatically be x % faster, just because Intel4 should allow x % more performance (which could be x % more frequency on the lower end of the V/f curve).

 

[DrMrLordX]

MTL doesn't even have to hit 6GHz to beat RPL. It just has to be at 5.5GHz.

I don't think even Raichu's leaked target v/f curve lists clockspeeds that high for Meteor Lake.

10nm and 10nm+ struggled to reach 4 GHz. Food for thought.

 

[A///]

This is so big, not even including the other 2 plants, or offices in Hillsboro, that it seems to be the new Silicon valley. Notices in the distance, thats Intel also.
View attachment 78055

This lets you zoom out and in to see the size. About 4 square miles of factories. Notice the airport , almost that size. And I don't know how recent these are, but the place is unimaginably huge. That one big building in the center is like 6 to 8 stories tall !

Intel-Ronler Acres Campus in Hillsboro, OR (Google Maps)

Intel-Ronler Acres Campus (Google Maps). On Dec. 8, 1994, Intel announced plans to begin the construction of Ronler Acres 1, a three-story 300,000 sq. ft. office building, and D1B, a 600,000 sq. ft. fab featuring a 35,000 sq. ft. cleanroom that would grow to 77,000 sq. ft. when converted into...

virtualglobetrotting.com

Also home to a murder. Someone got whacked a few weeks ago in the parking lot.

 

[uzzi38]

Correct, Lower SKUs will be rehash Raptor Lake

It's not a matter of lower vs higher end SKUs, it's better to think back to the Comet Lake and Ice Lake situation. Two seperate lineups.

EDIT: At the very least this is the case for mobile, idk about desktop

 

[Thunder 57]

@SiliconFly You should read some of the other posts before replying so confidently.

It's not possible cos I don't think Intel would work on their cpu tile on two different nodes at the same time! It's unprecedented. Never happened before!

Apple did it with one of their iPhones. Dual sourced from Samsung and TSMC. I suspect AMD looked in to it. They didn't trust GloFo for 7nm and yet switched to TSMC 7nm without missing a step. So either they never planned on GloFo 7nm or they were hedging their bets.

The MTL's Redwood Cove cores are getting a 20% PPW boost due to the node jump from Intel 7 -> Intel 4. Even if they're gonna use some of the gains (say 10%) for power efficiency, they'll still be left with 10% performance gain per core. And knowing Intel, they always prioritize performance over power consumption. So, MTLs cores are gonna be quite faster than RPL cores!

Nodes aren't always so great. AMD's 130nm was useless at first. TSMC's 20nm was largely ignored. Intel's 10nm was a disastor for a long time.

What I find very surprising is the fact that most people tend to forget the performance gains when an cpu core (logic) is moved from an old node to a more advanced node.

For example, Zen 3 was on TSMC N7P. And Zen 4 is on TSMC N4. Thats a one full node jump (slightly more actually). That gave Zen 4 upto 25% performance increase or upto 50% reduction in power (but not both) over Zen 3 due to the node jump alone. So, AMD chose 10% to 15% of the PPW budget for performance increase for Zen 4 and used the remaining PPW budget for power efficiency.

The increase in Zen 4 performance over Zen 3 is mostly not because of architectural changes, but mainly due to the node jump from TSMC N7 to N4.

What people forget is, the exact same advantage applies to Intel too.

Meteor Lake is shifting from Intel 7 to Intel 4. And it's a complete "full" node jump. Intel 4 offers upto 20% performance increase or upto 40% reduction in power (but not both) over Intel 7. If Intel uses the PPW budget properly, Meteor Lake will end up with 10% performance increase over RPL at a given frequency & will be 20% more power efficient than RPL.

Meaning, when it comes to IPC, Meteor Lake cpu @ 5.4GHz will be as fast as RPL cpu @ 6.0GHz.

MTL doesn't even have to hit 6GHz to beat RPL. It just has to be at 5.5GHz or slightly above. Thats all!

A counterargument: Intel's whole tick tock was based on the new node having almost no performance increase. Just a way to mature the node for the next "tock". More recently, Zen 2 to Zen 3 was a major leap forward, both were 7nm. RDNA1 to RDNA2 was a large leap ahead, again, both on 7nm.

Clock speed regression is always expected in a new node. Thats why I mentioned:

MTL doesn't even have to hit 6GHz to beat RPL. It just has to be at 5.5GHz.

And if they manage to bring in any new uArch performance improvements, that also adds up.

Even if they bring in a meager 5% uArch performance improvement to MTL over RPL, Meteor Lake will beat RPL at 5.2GHz

Intel has something excellent in its hand right now. Just wondering they don't eff it up like before!

Clock regression with a new node is a fairly new thing. In the past a new node would usually grant you nice increases immediately. The P4 was stuck at 2GHz on 180nm, but passed 3GHz on 130nm. It did so in about a year IIRC.

Also, since 1990 when it was 65k, the price of my house went up to 150k about 2011, and now its 475k due to all the Californians coming up here. One in 10 license plates is from California. The farm fields have disappeared. You should have seen this area in 1900. That picture you see ? other than farm fields it was the airport, and that was a lot smaller. Now its wall-to-wall factories and apartments.

Remember #CalExit? They are exiting all right, to plenty of other states!

 

[Hulk]

Intel's new cadence should be "tick tack toe."

"tick" is the mobile release of the new node on the old architecture
"tack" is the desktop release of the new node on the old architecture
"toe" is the new architecture release on the new node, now on 2nd update

 

[Thunder 57]

Intel's new cadence should be "tick tack toe."

"tick" is the mobile release of the new node on the old architecture
"tack" is the desktop release of the new node on the old architecture
"toe" is the new architecture release on the new node, now on 2nd update

I guess you missed the replacement to tick tock.

Intel’s ‘Tick-Tock’ Seemingly Dead, Becomes ‘Process-Architecture-Optimization’

www.anandtech.com

 

[LightningZ71]

It was noted in the past that some of the past Intel die shrinks that managed to tease out a few percent ipc gains on what was considered virtually the same logic design of the core were due to the shrink allowing some parts of the core to have improved latencies. When you shrink a design, you also shorten distances between various circuits inside of it, which reduces the observed charge propagation delay in getting a signal from one block to another. If you aren't ramping the clocks aggressively on the design, you can at least change some behaviors to take advantage of those reduced latencies. These are often highly case specific and get buried in instruction case averages. So, while an individual instruction sequence can see a 20% speedup because of this, the average instruction only improves a single percent or two because that sequence is averaged with thousands of other instruction sequences that see no change.

This is ONE way that a straight shrink can result in a marginal to minor IPC improvement when there is no actual change to the real circuit layout aside from process rule considerations. Also, going forward, the industry as a whole is seeing substantial issues with reducing the size of SRAM cells, which make up the various caches. Cache sizes on processors aren't going to skyrocket as a result of further shrinks. You might get a little more here and there as the core dimensions themselves shrink relative to previous generations, even with massive gains in circuit counts, as they still have roughly the same physical die size to work with. We're also getting into significant diminishing returns on desktop with physical core counts, save for specific industry use cases, which will make adding additional cores less of a gain.

 

[Geddagod]

I guess you missed the replacement to tick tock.

Intel’s ‘Tick-Tock’ Seemingly Dead, Becomes ‘Process-Architecture-Optimization’

www.anandtech.com

This was from 2016...
So it now doesn't take into account the 5 nodes in 4 years plan.
But even the proposed Tick Tack Toe cadence might not reflect the plan.
Golden Cove - desktop + mobile + server. Intel 7
Raptor Cove- GLC optimization on desktop + mobile +server. (because of delay)
Redwood Cove - GLC optimization on mobile first + desktop later? Intel 4
Redwood Cove + - RWC optimization on server. Intel 3
Lion Cove- new architecture, desktop first? + mobile. TSMC 3nm + Intel 20A
Panther Cove- new architecture, ultra low power mobile (lunar lake). TSMC 3nm or Intel 18A.
Panther Cove- desktop + mobile, prob Intel 18A
So starting from GLC, we go optimization, new node, new node, new node + new architecture, new architecture or new node+ new architecture, and then new node.

 

[Exist50]

This was from 2016...
So it now doesn't take into account the 5 nodes in 4 years plan.
But even the proposed Tick Tack Toe cadence might not reflect the plan.
Golden Cove - desktop + mobile + server. Intel 7
Raptor Cove- GLC optimization on desktop + mobile +server. (because of delay)
Redwood Cove - GLC optimization on mobile first + desktop later? Intel 4
Redwood Cove + - RWC optimization on server. Intel 3
Lion Cove- new architecture, desktop first? + mobile. TSMC 3nm + Intel 20A
Panther Cove- new architecture, ultra low power mobile (lunar lake). TSMC 3nm or Intel 18A.
Panther Cove- desktop + mobile, prob Intel 18A
So starting from GLC, we go optimization, new node, new node, new node + new architecture, new architecture or new node+ new architecture, and then new node.

There's also supposedly a Cougar Cove somewhere in the mix. Between Lion and Panther Cove, perhaps? Also, Lunar Lake is supposed to be Lion Cove + Skymont.

 

[Geddagod]

There's also supposedly a Cougar Cove somewhere in the mix. Between Lion and Panther Cove, perhaps? Also, Lunar Lake is supposed to be Lion Cove + Skymont.

Fg about that ye, raichu thinks that panther lake uses cougar cove not panther cove.
Lunar Lake intel claimed it was a fresh new architecture, so I assumed it was a fresh new architecture from the product behind it, LNL. But it could be new architecture in reference to GLC as well I guess.
It just makes so much sense for LNL to be the perfect pipe cleaner product on Intel 18A, it makes it hard for me to believe it would use TSMC instead. Plus PRQ in end of 2024 lines up with node readiness of Intel 18A in 2H 2024 to begin ramp.
In which case it would be:
optimization(RPL), new node(MTL), new node(GNR), new node + new architecture(ARL), optimization or optimization + new node(Intel 18A)?(LNL), and then new node + new architecture (PTL).

 

[Hulk]

It was noted in the past that some of the past Intel die shrinks that managed to tease out a few percent ipc gains on what was considered virtually the same logic design of the core were due to the shrink allowing some parts of the core to have improved latencies. When you shrink a design, you also shorten distances between various circuits inside of it, which reduces the observed charge propagation delay in getting a signal from one block to another. If you aren't ramping the clocks aggressively on the design, you can at least change some behaviors to take advantage of those reduced latencies. These are often highly case specific and get buried in instruction case averages. So, while an individual instruction sequence can see a 20% speedup because of this, the average instruction only improves a single percent or two because that sequence is averaged with thousands of other instruction sequences that see no change.

This is ONE way that a straight shrink can result in a marginal to minor IPC improvement when there is no actual change to the real circuit layout aside from process rule considerations. Also, going forward, the industry as a whole is seeing substantial issues with reducing the size of SRAM cells, which make up the various caches. Cache sizes on processors aren't going to skyrocket as a result of further shrinks. You might get a little more here and there as the core dimensions themselves shrink relative to previous generations, even with massive gains in circuit counts, as they still have roughly the same physical die size to work with. We're also getting into significant diminishing returns on desktop with physical core counts, save for specific industry use cases, which will make adding additional cores less of a gain.

Yes, but since the point of my post was to convince someone that process shrinks don't result in 10% or more IPC increase I thought that detail was de minimis and would obfuscate my primary point.

Do you have any examples of such IPC increases due solely to node shrinks? I'm not denying it as shorter paths would indicate less latency but there are a lot of inter-dependencies in the core to deal with so I'm not sure a die shrink would be all that need be done to capitalize on the shorter paths.

 

[LightningZ71]

My time in the industry is long past so I don't have any insider info anywhere. The concept was covered when I was getting my computer engineering degree and I remember reading about it in some past shrinks.

 

[SiliconFly]

I don't think even Raichu's leaked target v/f curve lists clockspeeds that high for Meteor Lake.

10nm and 10nm+ struggled to reach 4 GHz. Food for thought.

I just saw some weird predictions from MLID. He even quotes adored tv! And the predictions are completely off the mark! He says MTL is gonna have 20% IPC gains! I say BS. Are they really that bad at math OR are they just messing with us?

Everyone agrees or we instinctively know that the new Intel 4 node is going to have some clock-speed regression (even more maybe). And MTL has been going thru many iterations for more than a year now. Even if by miracle Intel hits 20% IPC architectural gains for Redwood Cove over Raptor Cove, they still have to deal with clock-speed regression which reduces the overall IPC of MTL.

We'll skip desktop parts for now & focus only on mobile. And let us assume, that MTL on Intel 4 somehow hits 5 GHz for their highest-end laptop offering. But RPL top-end laptop part runs at 5.6 GHz. So, thats a clock-speed regression of ~10% already (and this is possibly the best case scenario). It can be worse!

Like i said, even if the MTL architecture gains are 20%, MTL still loses 10% directly due to clock-speed regression. Which leaves it with just a 10% IPC gain over RPL (in the final product).

And all these numbers are best case scenarios for Intel. If we consider history, things have always been worse. In essence, we can expect a maximum of 10% IPC gains for MTL over RPL in reality. And that too ONLY IF Intel does many many things right.

So, where does this 20% IPC gains come from??? Or, apart from architectural gains, is MTL getting a huge bump in L2/L3 cache over RPL that only some are aware of?

 

[Geddagod]

I just saw some weird predictions from MLID. He even quotes adored tv! And the predictions are completely off the mark! He says MTL is gonna have 20% IPC gains! I say BS. Are they really that bad at math OR are they just messing with us?

Everyone agrees or we instinctively know that the new Intel 4 node is going to have some clock-speed regression (even more maybe). And MTL has been going thru many iterations for more than a year now. Even if by miracle Intel hits 20% IPC architectural gains for Redwood Cove over Raptor Cove, they still have to deal with clock-speed regression which reduces the overall IPC of MTL.

We'll skip desktop parts for now & focus only on mobile. And let us assume, that MTL on Intel 4 somehow hits 5 GHz for their highest-end laptop offering. But RPL top-end laptop part runs at 5.6 GHz. So, thats a clock-speed regression of ~10% already (and this is possibly the best case scenario). It can be worse!

Like i said, even if the MTL architecture gains are 20%, MTL still loses 10% directly due to clock-speed regression. Which leaves it with just a 10% IPC gain over RPL (in the final product).

And all these numbers are best case scenarios for Intel. If we consider history, things have always been worse. In essence, we can expect a maximum of 10% IPC gains for MTL over RPL in reality. And that too ONLY IF Intel does many many things right.

So, where does this 20% IPC gains come from??? Or, apart from architectural gains, is MTL getting a huge bump in L2/L3 cache over RPL that only some are aware of?

MLID supporting his claim from Adored TV is just not accurate, I think. The slide showed a power-perf improvement to bring 20% core performance improvement. Notice how they talk about how the power and performance improvements are bringing those gains... the word IPC was never mentioned anywhere in that slide. Sounds like those are the gains they expect from the node, to be more specific it sounds like the gains they expect from the node for each core in comparison to SPR.

 

[SiliconFly]

MLID supporting his claim from Adored TV is just not accurate, I think. The slide showed a power-perf improvement to bring 20% core performance improvement. Notice how they talk about how the power and performance improvements are bringing those gains... the word IPC was never mentioned anywhere in that slide. Sounds like those are the gains they expect from the node, to be more specific it sounds like the gains they expect from the node for each core in comparison to SPR.

We know very well that node gains don't usually translate well to IPC gains. Especially if the node is new and there's clock-speed regression. Even if MTL has architectural gains and a bump in L2/L3 cache, the best we can expect at this point is somewhere between 5% to 15% IPC gains.

My bet is single digit.

 

[Hitman928]

We know very well that node gains don't usually translate well to IPC gains. Especially if the node is new and there's clock-speed regression. Even if MTL has architectural gains and a bump in L2/L3 cache, the best we can expect at this point is somewhere between 5% to 15% IPC gains.

My bet is single digit.

I think @Geddagod is saying that MLID (and I guess Adored) are confusing perf/w improvement claims as IPC improvement claims. The actual claimed perf/w improvement is coming from the node thanks to lower power at the same frequency but these youtubers don't actually understand anything they talk about so they are thinking perf/w and IPC improvements are the same thing.

 

[Hulk]

I just saw some weird predictions from MLID. He even quotes adored tv! And the predictions are completely off the mark! He says MTL is gonna have 20% IPC gains! I say BS. Are they really that bad at math OR are they just messing with us?

Everyone agrees or we instinctively know that the new Intel 4 node is going to have some clock-speed regression (even more maybe). And MTL has been going thru many iterations for more than a year now. Even if by miracle Intel hits 20% IPC architectural gains for Redwood Cove over Raptor Cove, they still have to deal with clock-speed regression which reduces the overall IPC of MTL.

We'll skip desktop parts for now & focus only on mobile. And let us assume, that MTL on Intel 4 somehow hits 5 GHz for their highest-end laptop offering. But RPL top-end laptop part runs at 5.6 GHz. So, thats a clock-speed regression of ~10% already (and this is possibly the best case scenario). It can be worse!

Like i said, even if the MTL architecture gains are 20%, MTL still loses 10% directly due to clock-speed regression. Which leaves it with just a 10% IPC gain over RPL (in the final product).

And all these numbers are best case scenarios for Intel. If we consider history, things have always been worse. In essence, we can expect a maximum of 10% IPC gains for MTL over RPL in reality. And that too ONLY IF Intel does many many things right.

So, where does this 20% IPC gains come from??? Or, apart from architectural gains, is MTL getting a huge bump in L2/L3 cache over RPL that only some are aware of?

One things MTL and Intel 4 have going for them is the fact that at high clocks Raptor Lake has proven to be very hard to cool. For example, someone might bench at 5.1GHz and then again at 5.5GHz and not notice the mathematical increase in performance one would expect for the frequency increase even though HWinfo or Task Monitor shows "5.5GHz."

I believe that while "5.5GHz" might be displayed much of the time during the benchmark run the cores are actually bumping against throttling quite a bit, which isn't being accurately reported and this leads to the less and proportional increase in benchmarking stats.

I am mentioning this here because if MTL on Intel 4 eventually get to 5.5GHz all core at lower power levels these parts may well actually perform much better than similarly clocked Raptor Lake parts despite minimal IPC gains. You've probably noticed as I have that most reviews show the 13900K scoring around 38,000 CB R23 when at 5.5 it should be doing 40,000, which only a handful of reviews seem to be able to hit. Of course some of our expert underclockers around here have it this number

 

[Geddagod]

I think @Geddagod is saying that MLID (and I guess Adored) are confusing perf/w improvement claims as IPC improvement claims. The actual claimed perf/w improvement is coming from the node thanks to lower power at the same frequency but these youtubers don't actually understand anything they talk about so they are thinking perf/w and IPC improvements are the same thing.

Yes. Thank you. Sorry if it wasn't clear haha

 

[A///]

I just saw some weird predictions from MLID. He even quotes adored tv! And the predictions are completely off the mark! He says MTL is gonna have 20% IPC gains! I say BS. Are they really that bad at math OR are they just messing with us?

your first mistake was watching either of those two morons.

 

[IntelUser2000]

Design and Node can each provide different gains. If a node says "20% gain" you aren't limited to 20% equaling Density + Node. We got way, way more than that.

What's so awesome about nodes are that you don't need smarts to do so. Look at the rate of improvement for other industries. Car engines? Airplanes? They always have to use smarts. You can't just throw resources at it, you have to think, you have to innovate.

Things like Out of Order execution, Branch predictor algorithms, uop cache, those are innovations brought on by brilliant people that worked on improving CPUs for decades. Those are one-time improvements. Innovation is hard. Hard work is not enough, since everyone else is doing it. You need to think outside the box too.

But on computers you can have the exact same design, but a new node immediately provides 20% improvement. And you can better your design on top of that.

Just look at Tick/Tock. Tick provides the 10-20% gains, including perf/power and Tock provides additional 10-20% gains. When you combine them the gains far surpass node gains.

Clarkdale iGPU: 2x performance
Sandy Bridge iGPU: 2x performance
Ivy Bridge iGPU: 1.5-2x performance
Haswell: 30%
Broadwell 20%
Skylake: 25%
Icelake: 2x
Tigerlake: 2x

All at the same power level. Node-wise you are only talking 2x max?

 

[mikk]

There may have been some changes in Intel’s product planning for desktop computers. The previously rumored Meteor Lake-S, which was expected to launch in the first half of 2024, may be renamed Arrow Lake-S and paired with the Intel 800 series chipset. Both Meteor Lake-S and Arrow Lake-S use the Intel LGA 1851 socket.

According to the source, Arrow Lake-S will maintain a maximum 8P+16E core configuration, while the 6P+16E configuration for MTL-S will be canceled.

It is unclear whether these changes in desktop computer planning signify that Intel’s 20A process has completed relevant processes, as Arrow Lake-S uses this process. The expected launch date is in the first half of 2024.

Arrow Lake-S 平台回歸到 Intel 在 2024 桌上型電腦處理器產品規劃中 - BenchLife.info

Arrow Lake-S 的消息又跳出來了，而 Meteor Lake-S 現在可能消失。 Inte […]

benchlife.info

It's a little off I think. ARL-S on 20A during H1 2024 is not realistic. Maybe they are just assuming it's 20A because roadmaps usually don't say what node it uses. Or they are mixing it up with MTL-S. 6+16 cancelled, means 6+8 could still come.

 

[Geddagod]

Arrow Lake-S 平台回歸到 Intel 在 2024 桌上型電腦處理器產品規劃中 - BenchLife.info

Arrow Lake-S 的消息又跳出來了，而 Meteor Lake-S 現在可能消失。 Inte […]

benchlife.info

It's a little off I think. ARL-S on 20A during H1 2024 is not realistic. Maybe they are just assuming it's 20A because roadmaps usually don't say what node it uses. Or they are mixing it up with MTL-S. 6+16 cancelled, means 6+8 could still come.

Ye, ARL-S on 20a 1H 2024 is not realistic. Infact even 2H 2024 is definitely a stretch.
What's very interesting about the entire ARL situation is that Intel has been kinda hush about it- either that or they are behind on development.
Intel seemed pretty excited about taping in and powering on MTL, and I believe they announced the taping in of MTL in like a separate tweet without a corresponding event or anything IIRC.
ARL should have almost certainly taped in by now and we have heard zip.
As a side note though, I think this was pretty funny:
Gelsinger stated he was "somewhat amazed by some of these rumor mill discussions that come out".

 

[mikk]

They don't always announce the tape in/tapeout of future CPUs though, they did on Icelake and Meteor Lake. I'm not aware of other announcements in the past.

 

[Geddagod]

They don't always announce the tape in/tapeout of future CPUs though, they did on Icelake and Meteor Lake. I'm not aware of other announcements in the past.

I think they are certainly going to start doing it more, to reassure investors at this dire time for their company.
We know a bunch about dev cycle Granite Rapids too. IIRC we even saw a demo of GNR running at the end of 2022.