Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

[Tigerick]

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.



Comparison of upcoming Intel's U-series CPU: Core Ultra 100U, Lunar Lake and Panther Lake

Model	Code-Name	Date	TDP	Node	Tiles	Main Tile	CPU	LP E-Core	LLC	GPU	Xe-cores
Core Ultra 100U	Meteor Lake	Q4 2023	15 - 57 W	Intel 4 + N5 + N6	4	tCPU	2P + 8E	2	12 MB	Intel Graphics	4
?	Lunar Lake	Q4 2024	17 - 30 W	N3B + N6	2	CPU + GPU & IMC	4P + 4E	0	12 MB	Arc	8
?	Panther Lake	Q1 2026 ?	?	Intel 18A + N3E	3	CPU + MC	4P + 8E	4	?	Arc	12

Comparison of die size of Each Tile of Meteor Lake, Arrow Lake, Lunar Lake and Panther Lake

	Meteor Lake	Arrow Lake (N3B)	Lunar Lake	Panther Lake
Platform	Mobile H/U Only	Desktop & Mobile H&HX	Mobile U Only	Mobile H
Process Node	Intel 4	TSMC N3B	TSMC N3B	Intel 18A
Date	Q4 2023	Desktop-Q4-2024 H&HX-Q1-2025	Q4 2024	Q1 2026 ?
Full Die	6P + 8P	8P + 16E	4P + 4E	4P + 8E
LLC	24 MB	36 MB ?	12 MB	?
tCPU	66.48
tGPU	44.45
SoC	96.77
IOE	44.45
Total	252.15

Intel Core Ultra 100 - Meteor Lake



As mentioned by Tomshardware, TSMC will manufacture the I/O, SoC, and GPU tiles. That means Intel will manufacture only the CPU and Foveros tiles. (Notably, Intel calls the I/O tile an 'I/O Expander,' hence the IOE moniker.)

 

[Exist50]

Yup. But they only launched that as mobile only because 10nm was still not ready at that point . IIRC Tiger Lake launched as 4 core parts first and then 8 core parts, and never had exceptional volume until a while after launch too.

The 8c die's design was staggered after the 4c one. They probably could have used it for desktop, but at that point, wasn't worth the overhead of switching away from Rocket Lake. Remember that a 6c Rocket Lake mobile part was planned as well. That would have been a disaster.

 

[Exist50]

But Intel clearly mentioned ARL cpu is only Intel 20A then.

They have not. The current rumors suggest N3 for desktop and 20A for mobile.

 

[Exist50]

I think 5.5GHz is actually a pretty reasonable estimate for where we'll see Meteor Lake land. Heck, even for mobile chips. But obviously, that doesn't make for a particularly compelling desktop chip, assuming negligible IPC gains. I'm also rather worried about gaming performance with the MTL/ARL architecture. Gaming is quite sensitive to memory latency, and there's not just the move to chiplets, but also their SoC fabric has apparently seen a lot of change, and been the source of much trouble. Lost the main architect midway through, apparently. Even if Arrow Lake provides nice core gains, they might be muted by SoC considerations.

 

[SiliconFly]

How will MTL at 5.5 GHz beat RPL at 6 GHz without any architecture performance improvements? That makes zero sense.

A increase in density usually gives an opportunity to increase L2/L3 cache without any significant changes to the architecture. This in turn increases IPC. Meaning, more performance at the same frequency.

 

[SiliconFly]

I think 5.5GHz is actually a pretty reasonable estimate for where we'll see Meteor Lake land. Heck, even for mobile chips. But obviously, that doesn't make for a particularly compelling desktop chip, assuming negligible IPC gains. I'm also rather worried about gaming performance with the MTL/ARL architecture. Gaming is quite sensitive to memory latency, and there's not just the move to chiplets, but also their SoC fabric has apparently seen a lot of change, and been the source of much trouble. Lost the main architect midway through, apparently. Even if Arrow Lake provides nice core gains, they might be muted by SoC considerations.

MTL is Intel's first mainstream venture into chiplets (ignoring the now defunct Lakefield). And I'm sure it'll face a ton of issues. Thats why I mentioned a while ago that 2023 isn't Intel's year. AMD has a good chance to beat MTL this year. But, if Intel does things right, they may not fallback behind too much.

 

[Geddagod]

The 8c die's design was staggered after the 4c one. They probably could have used it for desktop, but at that point, wasn't worth the overhead of switching away from Rocket Lake. Remember that a 6c Rocket Lake mobile part was planned as well. That would have been a disaster.

Its a shame no one picked up the 11980HK on top of chinese motherboards and tried OCing it to the moon to compare perf at different wattages vs RKL (11900k).
Ik people have tested the 11900H online, but IIRC the 11980HK mobos has better VRMs and power delivery than the 11900H's mobos, so more OC potential. Cooling also was fine on the 11900H while OCing IIRC, so I don't think that would be an issue either.

 

[Geddagod]

So, in essence, switching to an advanced node will automatically give us better performance for the same architecture at the same frequency due to the extra logic, extra L2/L3 caches, better interconnects, etc

That makes it a different architecture though. Adding cache, adding extra logic, changing the interconnect, all of those would increase IPC and change the design (AKA new architecture). Therefore it's not the same architecture gaining performance at different frequencies, it's a new architecture gaining performance at different frequencies versus the old architecture.
The formula for Performance is simplistically Performance Per Clock X Clock (frequency).
When you move to a new node, you get a Clock (frequency) uplift, so more Performance.
When you change the caches, add extra logic, you get more Performance Per Clock (new architecture) so more Performance.
RWC at 5.5Ghz will not be as good as RPL at 6 GHz simply because of a new node if PPC did not increase. Because nodes aren't anywhere in the performance = PPC X Clock equation. All a new node does it help change either PPC or Clocks (or both). Unless RWC PPC increases, RWC could be on TSMC 2nm for all it matters, RWC at 5.5 GHz would performance worse than RPL at 6GHz.

 

[Hitman928]

Ok. I'll try a different approach. Here's a link to an anandtech article about power/performance/density of TSMC nodes for reference.

When a foundry says their node has 20% increase in performance per watt over previous generation, or 40% power savings over previous generation (but not both at the same time), they're usually talking about industry averages while using CPUs (with logic, cache, etc). In other words, the CPU gets upto 20% performance increase or upto 40% reduction in power (but not both) over the previous generation node for the same micro architecture (uArch).

Pls check the anandtech article above. Here's a link to another similar article by tomshardware. This article also talks about the node's "speed improvement", power savings & density.

The "speed improvement" or "performance increase" numbers advertised by the nodes like TSMC, Samsung, Intel is typically based on CPUs (logic). They calculate it based on power, performance & density. For example, TSMC N3 will be upto 15% faster than N5 for the same power and given the same area (when they say same area, they're talking about increase in caches/interconnects due to the additional transistors in the die because of the increase in density). This was mentioned by TSMC CEO himself when questioned by journalists. And this measure (PPW, PPA or power/performance/density) has been spot on for the nodes for many years now. Even though it's a estimate based on averages, it's still the best measure for the nodes at the moment.

So, in essence, switching to an advanced node will automatically give us better performance for the same architecture at the same frequency due to the extra L2/L3 caches, interconnects, logic, etc.

You are confused about how this works. When a foundry is advertising performance increases, they are talking about frequency, that is how the "performance" of a node is judged, along with density and power use. Compute performance per Hz is entirely design dependent so when you mention changing things like caches and adding transistors to the die, that is changing the architecture. If you take the exact same architecture and "shrink" it by putting it on a more advanced node, it will have the same performance per Hz but will either run at a higher frequency or lower power (or both). This happens occasionally, a great example is in gaming consoles. Since consoles have long life spans (in the tech world), console makers will plan on having the same chips ported to a new node. They have the same performance, but are now cheaper per chip (due to improved density) and lower power which allows them to also use cheaper supporting components (e.g. power supply) and shrink the size of the overall console.

 

[SiliconFly]

You are confused about how this works. When a foundry is advertising performance increases, they are talking about frequency, that is how the "performance" a node is judged, along with density and power use. Compute performance per Hz is entirely design dependent so when you mention changing things like caches and adding transistors to the die, that is changing the architecture. If you take the exact same architecture and "shrink" it by putting it on a more advanced node, it will have the same performance per Hz but will either run at a higher frequency or lower power (or both). This happens occasionally, a great example is in gaming consoles. Since consoles have long life spans (in the tech world), console makers will plan on having the same chips ported to a new node. They have the same performance, but are now cheaper per chip (due to improved density) and lower power which allows them to also use cheaper supporting components (e.g. power supply) and shrink the size of the overall console.

That sounds right. Thanks for the info.

 

[Hulk]

Ok. I'll try a different approach. Here's a link to an anandtech article about power/performance/density of TSMC nodes for reference.

When a foundry says their node has 20% increase in performance per watt over previous generation, or 40% power savings over previous generation (but not both at the same time), they're usually talking about industry averages while using CPUs (with logic, cache, etc). In other words, the CPU gets upto 20% performance increase or upto 40% reduction in power (but not both) over the previous generation node for the same micro architecture (uArch).

Pls check the anandtech article above. Here's a link to another similar article by tomshardware. This article also talks about the node's "speed improvement", power savings & density.

The "speed improvement" or "performance increase" numbers advertised by the nodes like TSMC, Samsung, Intel is typically based on CPUs (logic). They calculate it based on power, performance & density. For example, TSMC N3 will be upto 15% faster than N5 for the same power and given the same area (when they say same area, they're talking about increase in caches/interconnects due to the additional transistors in the die because of the increase in density). This was mentioned by TSMC CEO himself when questioned by journalists. And this measure (PPW, PPA or power/performance/density) has been spot on for the nodes for many years now. Even though it's a estimate based on averages, it's still the best measure for the nodes at the moment.

So, in essence, switching to an advanced node will automatically give us better performance for the same architecture at the same frequency due to the extra L2/L3 caches, interconnects, logic, etc.

I sense this topic going off the rails. Let's put it back on the rails. Here are the specific points I'm addressing.

First, It is unlikely for Meteor Lake to hit 5.5GHz upon release in 2023. That node may well eventually reach 5.5GHz and beyond. But, based on Intel process history (detailed below) it is highly doubtful Intel will get there with it's first crack at Intel 4.

Second, node shrinks alone of an architecture bring no IPC gains to the underlying architecture. Overall performance may be increased but only through increasing frequency, which as I will demonstrate generally takes a few process revisions.

Let's look recent Intel process history.
65nm topped out at 3GHz
45nm topped out at 3.76GHz and it took a generation to get there.
32nm topped out at 4GHz and also took a generation to get there.
22mm topped out at 4.4GHz and took a generation to get there, first crack was 3.9GHz.
14nm topped out at 5.3GHz. It started at 3.7GHz and took over 5 years and many "+" generations to reach 5.3GHz. This is where the real trouble with Intel's process plans began.
10nm topped out (so far) at 6GHz. But it started at 3.2GHz if you count Canon Lake before reaching 6GHz with Raptor Lake, 5 years later. Also keep in mind that it took a whole year to get 10nm from 3.2GHz to 4.1GHz with Ice Lake, and another year to reach 4.8GHz with Tiger Lake, another year to 5.5GHz with Alder and yet another to 6GHz with Raptor. As you can see the time intervals remained relatively constant (~1 year) while the frequency ramps decreased, as expected. It gets harder to squeeze more out of the node.

Now let's look at how frequency increased from node-to-node when Intel was finally finished with a node and moved on.

65nm to 45nm === 760MHz increase
45nm to 32nm===240MHz increase
32nm to 22nm===400Mhz increase
22nm to 14nm===900MHz increase (5 years)
14nm to 10nm===600MHz increase (5 years)

The point here is that I (based on past Intel history, not marketing slides projecting performance) don't think Intel is capable of releasing Meteor Lake on Intel 4 at 5.5GHz in 2023. It's just much to expect based on history for the first crack at a new node. Furthermore, if Meteor Lake IPC gains are minimal as IntelUser2000 believes, then in order to release Meteor on the desktop clocks would actually have to match current Raptor clocks, which as we all know are beyond 5.5GHz.

Intel has demonstrated in the past with 14nm Broadwell and 10nm Ice Lake that they can recoup some of the costs of the new node by releasing mobile parts at lower clocks, which can perform better than the new node in terms of power at ISO frequencies until the process is refined enough to reach desktop frequencies of the previous node.

So this is why I and many around here believe Intel is doing exactly what it did with the first 14nm and10nm parts by releasing them first only in mobile form.

Now could I be wrong? Certainly! It would be fantastic to see Intel bring out the first sellable Intel 4 products hitting 5.5GHz. But looking at the actual history as noted above makes that scenario very unlikely.

 

[igor_kavinski]

Lost the main architect midway through, apparently.

Hey! You can't just drop that juicy bit in your post and not elaborate. Did that person die? If not, who poached The Arkitact?

 

[A///]

I always saw Lakefield as Intel's toe in the water for chiplet design among others like being a hybrid design, before jumping head first naked into the pool of swimming sharks.

 

[Exist50]

Hey! You can't just drop that juicy bit in your post and not elaborate. Did that person die? If not, who poached The Arkitact?

I never asked about him in particular, but very high probability it was Microsoft. They set up a new team in the Portland area around 2020/2021, I want to say, and "poached" an enormous number of engineers from Intel's Oregon design team, i.e. the people working on Meteor Lake. Though a lot of senior folk apparently left in general, not just to Microsoft. One of several reasons I keep harping on Meteor Lake being a dumpster fire from the design side, and why I've been skeptical about attributing all the blame for its delays to the process side.

 

[igor_kavinski]

Intel, who you gonna call?

Intel ISRAEEEEEEEELLLLLL!!!!

 

[Markfw]

This is so big, not even including the other 2 plants, or offices in Hillsboro, that it seems to be the new Silicon valley. Notices in the distance, thats Intel also.


This lets you zoom out and in to see the size. About 4 square miles of factories. Notice the airport , almost that size. And I don't know how recent these are, but the place is unimaginably huge. That one big building in the center is like 6 to 8 stories tall !

Intel-Ronler Acres Campus in Hillsboro, OR (Google Maps)

Intel-Ronler Acres Campus (Google Maps). On Dec. 8, 1994, Intel announced plans to begin the construction of Ronler Acres 1, a three-story 300,000 sq. ft. office building, and D1B, a 600,000 sq. ft. fab featuring a 35,000 sq. ft. cleanroom that would grow to 77,000 sq. ft. when converted into...

virtualglobetrotting.com

 

[eek2121]

What I find very surprising is the fact that most people tend to forget the performance gains when an cpu core (logic) is moved from an old node to a more advanced node.

For example, Zen 3 was on TSMC N7P. And Zen 4 is on TSMC N4. Thats a one full node jump (slightly more actually). That gave Zen 4 upto 25% performance increase or upto 50% reduction in power (but not both) over Zen 3 due to the node jump alone. So, AMD chose 10% to 15% of the PPW budget for performance increase for Zen 4 and used the remaining PPW budget for power efficiency.

The performance increase is an average used by foundries for cpu logic mostly. And it just works as explained by TSMC CEO himself. It includes performance increase due to additional logic and caches in the die due to increase in logic density. And not just frequency alone!!!!!!!!!!!!!

The increase in Zen 4 performance over Zen 3 is mostly not because of architectural changes, but mainly due to the node jump from TSMC N7 to N4.

What people forget is, the exact same advantage applies to Intel too.

Meteor Lake is shifting from Intel 7 to Intel 4. And it's a complete "full" node jump. Intel 4 offers upto 20% performance increase or upto 40% reduction in power (but not both) over Intel 7. If Intel uses the PPW budget properly, Meteor Lake will end up with 10% performance increase over RPL at a given frequency & will be 20% more power efficient than RPL.

Meaning, when it comes to IPC, Meteor Lake cpu @ 5.4GHz will be as fast as RPL cpu @ 6.0GHz.

MTL doesn't even have to hit 6GHz to beat RPL. It just has to be at 5.5GHz or slightly above. Thats all!

Zen 4 is on TSMC N5, not N4. Also, AMD played loosey goosey with the tech, with densities of the chiplets reaching N7 tops.

Intel has had no issue scaling clocks above and beyond the previous node, just like AMD.

 

[eek2121]

This is so big, not even including the other 2 plants, or offices in Hillsboro, that it seems to be the new Silicon valley. Notices in the distance, thats Intel also.
View attachment 78055

This lets you zoom out and in to see the size. About 4 square miles of factories. Notice the airport , almost that size. And I don't know how recent these are, but the place is unimaginably huge. That one big building in the center is like 6 to 8 stories tall !

Intel-Ronler Acres Campus in Hillsboro, OR (Google Maps)

Intel-Ronler Acres Campus (Google Maps). On Dec. 8, 1994, Intel announced plans to begin the construction of Ronler Acres 1, a three-story 300,000 sq. ft. office building, and D1B, a 600,000 sq. ft. fab featuring a 35,000 sq. ft. cleanroom that would grow to 77,000 sq. ft. when converted into...

virtualglobetrotting.com

Regardless of certain positions here by anyone (including myself), I think it is neat that those factories contain some of the most cutting edge tech in the world! I make a very good living for myself, but I've not made it out that way (to the pacific nw in general) despite really wanting to. I keep coming up with excuses, but I really need to visit. Thanks for the street view pics.

 

[moinmoin]

What people forget is, the exact same advantage applies to Intel too.

So is Intel changing to TSMC N5 as well, or why do you think the exact same advantage applies? Intel more than ever has to prove its node is competitive to TSMC, and its design is competitive to AMD. Both at once.

 

[Markfw]

Regardless of certain positions here by anyone (including myself), I think it is neat that those factories contain some of the most cutting edge tech in the world! I make a very good living for myself, but I've not made it out that way (to the pacific nw in general) despite really wanting to. I keep coming up with excuses, but I really need to visit. Thanks for the street view pics.

Also, since 1990 when it was 65k, the price of my house went up to 150k about 2011, and now its 475k due to all the Californians coming up here. One in 10 license plates is from California. The farm fields have disappeared. You should have seen this area in 1900. That picture you see ? other than farm fields it was the airport, and that was a lot smaller. Now its wall-to-wall factories and apartments.

 

[scannall]

Also, since 1990 when it was 65k, the price of my house went up to 150k about 2011, and now its 475k due to all the Californians coming up here. One in 10 license plates is from California. The farm fields have disappeared. You should have seen this area in 1900. That picture you see ? other than farm fields it was the airport, and that was a lot smaller. Not its wall-to-wall factories and apartments.

My Grandfather was a boy when their family immigrated to San Jose in 1906. Very small agricultural town. Rickety buildings, dusty streets. Not a trace of San Jose's roots remains.

 

[IntelUser2000]

You are confused about how this works. When a foundry is advertising performance increases, they are talking about frequency, that is how the "performance" of a node is judged, along with density and power use.

You are right in the big picture but, technically when they talk about "performance" for a node, they are talking about transistor drive current.

That doesn't necessarily translate into clocks, especially when clocks are insane like 5.5GHz+.

And all this kinda annoys me. Who cares about something that's 5% faster when it'll be behind AMD and when they have to delay the BIG THING(TM) to do so?

It is in Intel's BEST interests to can Meteorlake desktop to hasten Arrowlake, because not only you get newer designs, you get N3/20A faster. If you had full on Meteorlake desktop, then 20A gets needlessly delayed. For what? Something that would end up equal to a $299 Zen 5 chip?

Obviously Intel knew that Meteorlake-S would be disappointing. People were impressed about Raptorlake because of the 30%+ performance gain not the power efficiency. So was Alderlake. They cannot charge more money for a chip that's 20%+ slower than the competition.

Death to Meteorlake Desktop.

And I never said 1% as being the concrete number.

 

[itsmydamnation]

And I said 1% as being the concrete number.

 

[jpiniero]

It is in Intel's BEST interests to can Meteorlake desktop to hasten Arrowlake, because not only you get newer designs, you get N3/20A faster. If you had full on Meteorlake desktop, then 20A gets needlessly delayed.

That's not how it works. Not releasing Meteor Lake-S isn't going to make Arrow Lake come sooner. It means you get Raptor Lake Refresh instead.

 

[Hulk]

And I never said 1% as being the concrete number.

I apologize if I gave the impression you said this.

I should have been more clear in that you heard that MTL IPC over Raptor could be as low as 1%.

 

[Exist50]

You are right in the big picture but, technically when they talk about "performance" for a node, they are talking about transistor drive current.

Nah, they typically do refer to clock speed. Occasionally they'll even show the curves where they derive it from. Of course, usually that number is arrived at by extremely tortured comparisons.