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Discussion Intel Meteor, Arrow, Lunar & Panther Lakes + WCL Discussion Threads

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Tigerick

Senior member
Wildcat Lake (WCL) Specs

Intel Wildcat Lake (WCL) is upcoming mobile SoC replacing Raptor Lake-U. WCL consists of 2 tiles: compute tile and PCD tile. It is true single die consists of CPU, GPU and NPU that is fabbed by 18-A process. Last time I checked, PCD tile is fabbed by TSMC N6 process. They are connected through UCIe, not D2D; a first from Intel. Expecting launching in Q1 2026.

Intel Raptor Lake UIntel Wildcat Lake 15WIntel Lunar LakeIntel Panther Lake 4+0+4
Launch DateQ1-2024Q2-2026Q3-2024Q1-2026
ModelIntel 150UIntel Core 7 360Core Ultra 7 268VCore Ultra 7 365
Dies2223
NodeIntel 7 + ?Intel 18-A + TSMC N6TSMC N3B + N6Intel 18-A + Intel 3 + TSMC N6
CPU2 P-core + 8 E-cores2 P-core + 4 LP E-cores4 P-core + 4 LP E-cores4 P-core + 4 LP E-cores
Threads12688
Max Clock5.4 GHz4.8 GHz5 GHz4.8 GHz
L3 Cache12 MB6 MB12 MB12 MB
TDP15 - 55 W15 - 35 W17 - 37 W25 - 55 W
Memory128-bit LPDDR5-520064-bit LPDDR5x-7467128-bit LPDDR5x-8533128-bit LPDDR5x-7467
Size96 GB48 GB32 GB128 GB
Bandwidth83 GB/s60 GB/s136 GB/s120 GB/s
GPUIntel GraphicsIntel GraphicsArc 140VIntel Graphics
RTNoNoYESYES
EU / Xe96 EU2 Xe8 Xe4 Xe
Max Clock1.3 GHz2.6 GHz2 GHz2.5 GHz
NPUGNA 3.017 TOPS48 TOPS49 TOPS






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As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.



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Last edited:
It got deleted but it will be announced officially in a few hours.

ARL-S
5.7ghz 1T boost clocks
5.4ghz nT boost clocks
4.6ghz e-core clocks

Z890 boards at computex are shown to be supporting CAMM2 memory.

As of now it appears that
Thanks. Clocks are a bit better than expected. I was thinking 10% regression. This is more like 5% and of course an increase for Skymont, which makes me think there was a big architectural overhaul for Skymont.

Okay, seems like they've got the clocks. Now they need that enormous IPC increase on Skymont, at least 10% on Lion Cove, and some efficiency/power improvements.
 
Last edited:
It got deleted but it will be announced officially in a few hours.

ARL-S
5.7ghz 1T boost clocks
5.4ghz nT boost clocks
4.6ghz e-core clocks

Z890 boards at computex are shown to be supporting CAMM2 memory.

As of now it appears that
Dang, kudos to Intel if true.
 
What stops e.g. Z790 from using CAMM2?
I thought MSI showed off such a thing.
What I meant was since Intel makes you upgrade every 2 generations, that means you have to get a new motherboard along with your new CPU and this time ARL boards come with newer memory standards.

AM5 will last a long time and most Zen 4 users will likely not upgrade their motherboard because of AMDs long platform support. There are advantages to both strategies. If I had to choose I would prefer AM5, cause motherhood upgrades are a pain. I prefer a CPU upgrade on the same platform unless the other team brings massive improvements.
 
If it didn't take me 15 hours, I'd be making a "The Arrow Lake Hype Tomb" video right now.
I'm not telling you not to believe, believe all you like. Just remember, hype trains crash, ours just did, and hype mines sometimes crumble on you too.
Yes it would be Indiana Jones based. I could probably make a great scene of Pat pulling the heart out of the P Core dev team screaming KALI MAAAAAAAA
Screenshot 2024-06-03 202347.png
 

Intel announced AI Playground for Arc Graphics (>8GB VRAM) and Arc Graphics integrated (>= 16GB RAM) from Lunar Lake and beyond( except MTL-U, ARL-U and ARL-S/HX due to usage of XMX)
 
skymont-17-.png


Chadmont in action.
 
Also, not too sure about calling a 4-cyc 48K d-cache an "L0" but maybe there's something I'm missing. Their "L0" sounds to me very much like an L1, and their "L1" sounds very much like an L2.
 
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