Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

[Tigerick]

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.





Intel Core Ultra 100 - Meteor Lake



As mentioned by Tomshardware, TSMC will manufacture the I/O, SoC, and GPU tiles. That means Intel will manufacture only the CPU and Foveros tiles. (Notably, Intel calls the I/O tile an 'I/O Expander,' hence the IOE moniker.)

 

[adroc_thurston]

So LNL is using a 4P+4E configuration.

Yes it's a not-Apple tablet part.

That wouldn't be very strong in Multithreaded. Are we expecting huge ST gains?

It's a 10W tablet chip stretched far above where it should be, so no.

 

[Thunder 57]

I swear to god
dunno where the w came from, but it just felt right lol

I have sort of subscribed to Elon Musk's POV that acronyms suck unless they are widely known. I saw what you wrote and it looked sort of familiar, but couldn't figure it out. So I searched for it and got nowhere. That's why I came back to ask. At least you were a good sport about it . The W just felt right lol.

It is interesting that Intel is using N3 for CPU tiles. I'm guessing that means either 18A is late or that it doesn't do well in low power (seems unlikely).

 

[mikk]

8533 MT/s offers 33% higher BW, but that alone means nothing.
You need to know the performance of both IGPs and If they are bottlenecked or not.
The amount of Xe is the same.
IGP's architectural gain is unknown.
LNL with 8Xe will be clocked at 1850MHz, that's not particularly high for a 30W chip.
For example, 7840U at 25W manages 1833MHz in Witcher, but has less execution units(768 vs 1024).

It will be interesting to compare It to Strix Point limited to 30W, which will have a comparable 16CU(1024FP32) IGP.

We don't know the final clock speeds and probably even Intel can't know 1 year before release. There is a 8W sample running at 1.5 Ghz on Sisoft, 1850 Mhz might be realistic for 17W therefore. MTL-H 28W boosts to 2250 Mhz. MTL should support LPDDR5x-7500, at least MTL-H. Maybe MTL-M only supports LP5-6400 but doesn't really matter with only 64 SIMD8 EUs.

 

[capricornsunvoyager2]

I'm confused as to why Intel is using TSMC for the compute tile. I very much expected graphics and/or I/O dies to be made by TSMC. I don't get how people are spinning this as being just fine. What happened to 5 nodes in 4 years?

I understand that the compute tile, the CPU, will be done in Intel nodes always, but the SOC and the GPU will be TSMC.

 

[mikk]

I understand that the compute tile, the CPU, will be done in Intel nodes always, but the SOC and the GPU will be TSMC.

CPU+GPU is one tile using TSMC N3B.

 

[H433x0n]

I'm confused as to why Intel is using TSMC for the compute tile. I very much expected graphics and/or I/O dies to be made by TSMC. I don't get how people are spinning this as being just fine. What happened to 5 nodes in 4 years?

MTL uses TSMC’s N6 on the SoC & IO tile.. does this mean there’s something wrong with Intel 7 now?

Both GNR & SRF are using Intel 3. Why would they do that if they’re tacitly admitting N3B is better than anything they have with LNL? Data Center is where they’re the farthest behind AMD- why wouldn’t they use TSMC to level the playing field with Genoa & Turing?

People are looking into this to confirm prior biases. All nuance is thrown out the window.

 

[adroc_thurston]

why wouldn’t they use TSMC to level the playing field with Genoa & Turing?

because it won't help.
IDM magick at least lets them compete on costs.

 

[H433x0n]

because it won't help

That doesn’t makes sense. The further you are behind the more tempting and beneficial it’d be to use the best available node.

Edit: Lower costs are sort of a secondary concern when you’re so far behind on power efficiency. I’m sure Intel would gladly trade 20% higher costs for 20% more power efficiency with SPR.

 

[itsmydamnation]

That doesn’t makes sense. The further you are behind the more tempting and beneficial it’d be to use the best available node.

Thats a very simplistic view of a complex problem for Intel , fab costs aren't linear to wafer throughout. Will Intel make more margin using tmsc with both the increase cost of using tmsc but also the reduced wafers on Intel fabs increasing the production cost of there remaining wafers.

 

[Thunder 57]

MTL uses TSMC’s N6 on the SoC & IO tile.. does this mean there’s something wrong with Intel 7 now?

Both GNR & SRF are using Intel 3. Why would they do that if they’re tacitly admitting N3B is better than anything they have with LNL? Data Center is where they’re the farthest behind AMD- why wouldn’t they use TSMC to level the playing field with Genoa & Turing?

People are looking into this to confirm prior biases. All nuance is thrown out the window.

But MTL is using Intel 4 for the CPU, right? Not sure what you are getting at.

 

[adroc_thurston]

The further you are behind the more tempting and beneficial it’d be to use the best available node.

If you're fabless, yea.
But chungus server parts keep fab utilization high.

Lower costs are sort of a secondary concern when you’re so far behind on power efficiency

Cost is the only way for Intel to compete in server, they're the poor people brand.
SPR-MCC isn't the best thing out there but it's cheap and thus, good enough.

 

[H433x0n]

Thats a very simplistic view of a complex problem for Intel , fab costs aren't linear to wafer throughout. Will Intel make more margin using tmsc with both the increase cost of using tmsc but also the reduced wafers on Intel fabs increasing the production cost of there remaining wafers.

I agree that’s it’s nuanced. I’m trying to point out the nuance and contradictions of logic with my posts.

DC chips are likely the least sensitive to wafer costs fwiw.

But MTL is using Intel 4 for the CPU, right? Not sure what you are getting at.

Using your logic - Does that mean Intel 4 is better than N5?

It’s more nuanced than what is being portrayed in the past few pages. There’s more factors involved than just choosing the “best” process tech. Costs, performance, yield, availability and existing contracts are all a factor. I’ll drop it though since I’m sure this topic will be brought up regularly to dunk on IFS for the next 2 years.

 

[Thunder 57]

I agree that’s it’s nuanced. I’m trying to point out the nuance and contradictions of logic with my posts.

DC chips are likely the least sensitive to wafer costs fwiw.


Using your logic - Does that mean Intel 4 is better than N5?

Considering we have yet to see MTL it is impossible to say. I would expect Intel 4 to be better than N5.

 

[H433x0n]

Considering we have yet to see MTL it is impossible to say. I would expect Intel 4 to be better than N5.

If that were the case then 20A would easily outperform N3B since it’s only theoretically like ~10% better than N4P.

I don’t think any of what I wrote above is true. I’m not sure Intel 4 will outperform N5P/N4P nor do I think 20A will easily outperform N3B/N3E. I’m merely pointing out that this a very poor metric of determining which node is “best”.

 

[FlameTail]

If that were the case then 20A would easily outperform N3B since it’s only theoretically like ~10% better than N4P.

N4P and N3B are near identical in power and performance metrics. The only significant advantage of N3B is it's density.

 

[Joe NYC]

Should they hold off another 6-9 months on Lunar Lake so it can be fab'd on 18A for better PR and internet points or launch their mobile processor on a very efficient TSMC N3 node? It seems you're suggesting the former.

Instead of TSMC N3b, Intel can use "Intel 3" or 20A.

Intel is claiming that both of these nodes will be ready Intel implies these nodes are comparable.

 

[tamz_msc]

Intel is claiming that both of these nodes will be ready Intel implies these nodes are comparable.

"Ready" doesn't remotely mean comparable.

 

[Joe NYC]

10% chip density for a solid chungus wafer price bump is not something anyone outside of DC can afford.
Only products like venice-dense are viable on vanilla N2.

If Apple started doing real chiplets, and offloaded analog and SRAM to a cheaper node (only keeping logic on the most advanced node) then the density increase would be greater.

 

[Joe NYC]

"Ready" doesn't remotely mean comparable.

"Ready" for manufacturing
"Comparable" in specs / performance

 

[tamz_msc]

"Ready" for manufacturing
"Comparable" in specs / performance

Not even close. 20A is ribbonFET, 3 is still FinFET.

 

[adroc_thurston]

If Apple started doing real chiplets, and offloaded analog and SRAM to a cheaper node (only keeping logic on the most advanced node) then the density increase would be greater.

TSM quotes "chip-level" density bump which is like 50% logic 30% SRAM 20% analog or w/ever the metric so density will be awful either way.
Also "chiplet" still means PHY city my man, see Elk Range AID.

 

[Geddagod]

Instead of TSMC N3b, Intel can use "Intel 3" or 20A.

Intel is claiming that both of these nodes will be ready Intel implies these nodes are comparable.

Highly, Highly, Highly doubt Intel 3 is going to be comparable to TSMC N3. Especially with how important SRAM density is becoming... I mean I think it's going to be better than TSMC N4, but still...
There's a reason even Intel is claiming they won't have foundry leadership until 18A.

As for 20A, Intel is using 20A for ARL. They have confirmed that themselves. Problem is prob capacity, and also prob a bit of risk aversion by diversifying the nodes they use.

 

[Joe NYC]

TSM quotes "chip-level" density bump which is like 50% logic 30% SRAM 20% analog or w/ever the metric so density will be awful either way.

Exactly. Chip level density increase.

I have seen some comparisons between nodes that break out logic density, and that scaling is a much bigger number, while analog and SRAM approaching zero scaling.

So if Apple were to start using chiplets, then Apple could get higher density increase from the N2 node.

Also "chiplet" still means PHY city my man, see Elk Range AID.

But that's N6, which is the place to move the non-scalable elements. Hopefully, AMD is negotiating good rates on N6, since TSMC utilization is still in the toilet on this node..

And AMD may be becoming #1 customer on the N6/N7 node...

 

[Joe NYC]

Highly, Highly, Highly doubt Intel 3 is going to be comparable to TSMC N3. Especially with how important SRAM density is becoming... I mean I think it's going to be better than TSMC N4, but still...
There's a reason even Intel is claiming they won't have foundry leadership until 18A.

As for 20A, Intel is using 20A for ARL. They have confirmed that themselves. Problem is prob capacity, and also prob a bit of risk aversion by diversifying the nodes they use.

The N3B is not the best node. And SRAM scaling is very low there. Intel could use either one of the nodes I mentioned, even if it is a cost of a percentage decrease in performance or power.

Capacity (especially EUV capacity) may be an issue Intel is facing, but TSMC slowed down delivery of some equipment, so Intel could grab some of that, if the capacity was the issue.

Or, it could be (as Hillary Clinton famously said) a "public" position on an issue and "private" position.

Public being the one Gelsinger uses as a pep-talk (to customers, Wall Street, employees) and private position is what Intel really believes about readiness and competitiveness of the new nodes.

 

[H433x0n]

Highly, Highly, Highly doubt Intel 3 is going to be comparable to TSMC N3. Especially with how important SRAM density is becoming... I mean I think it's going to be better than TSMC N4, but still...
There's a reason even Intel is claiming they won't have foundry leadership until 18A.

The difference between N4P and N3B/N3E is small. I can’t find TSMC marketing material that compares N4P vs N3B or N3E directly. It’s like ~5-8% performance improvement with better density. If Intel 3 matches or exceeds N4P performance then practically speaking it’s comparable.

Even factoring in sram density assuming that Intel 3 has no improvements over Intel 4 sram cells then it’s 0.0240 vs 0.0210 (N3E) - it’s not that far off.