Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

[Tigerick]

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.





Intel Core Ultra 100 - Meteor Lake



As mentioned by Tomshardware, TSMC will manufacture the I/O, SoC, and GPU tiles. That means Intel will manufacture only the CPU and Foveros tiles. (Notably, Intel calls the I/O tile an 'I/O Expander,' hence the IOE moniker.)

 

[itsmydamnation]

x86 SunnyCove failed? What? SunnyCove is a redesigned and expanded core that has 38% more transistors than SkyLake. Despite still having 4-way decoding and 4 ALUs, it has an average of 18% higher IPC. Zen 3 with 19% IPC increase is a huge profit, and SunnyCove with 18% higher IPC is already a failed architecture? Really?

talk about picking and choosing ,

So Zen 2->3,
rob 224 -> 256 , an increase of 32 entries
L1D cache 32kb -> 32kb , 0 increase
decode 4 -> 4
ALU 4 -> 4 0 increase
load 2 -> 3 ( no additional AGU or memory pipelines)
store 1->2 ( no additional AGU or memory pipelines)

skylake -> Sunny cove
rob 224 -> 352 , increase of 128 entries !!!!!!!!
L1D cache 32kb -> 48k , 50% increase
decode 3+1 -> 4+ 1 , extra decode unit
ALU 4 -> 4 0 increase
load 2 -> 2
store 1 -> 2 , 100% increase extra AGU and pipeline

Intel had to spend big in brute force adding of raw resources relative to AMD to get an equivalent level of performance increase, if you look at Zen3 AMD significantly increased utilisation of existing units by changing scheduling arrangements, sharing PRF ports and sharing of load/store ports/agu's. Now that's powder AMD still have dry and intel have spent, we will see what that powder looks like in a few months time.

Both Sunny and Golden cove aren't bad performing cores. But there not great relative to cores that spend the same level of architectural resources or get the same level of performance with significantly less spending.

 

[Henry swagger]

talk about picking and choosing ,

So Zen 2->3,
rob 224 -> 256 , an increase of 32 entries
L1D cache 32kb -> 32kb , 0 increase
decode 4 -> 4
ALU 4 -> 4 0 increase
load 2 -> 3 ( no additional AGU or memory pipelines)
store 1->2 ( no additional AGU or memory pipelines)

skylake -> Sunny cove
rob 224 -> 352 , increase of 128 entries !!!!!!!!
L1D cache 32kb -> 48k , 50% increase
decode 3+1 -> 4+ 1 , extra decode unit
ALU 4 -> 4 0 increase
load 2 -> 2
store 1 -> 2 , 100% increase extra AGU and pipeline

Intel had to spend big in brute force adding of raw resources relative to AMD to get an equivalent level of performance increase, if you look at Zen3 AMD significantly increased utilisation of existing units by changing scheduling arrangements, sharing PRF ports and sharing of load/store ports/agu's. Now that's powder AMD still have dry and intel have spent, we will see what that powder looks like in a few months time.

Both Sunny and Golden cove aren't bad performing cores. But there not great relative to cores that spend the same level of architectural resources or get the same level of performance with significantly less spending.

Golden is superior to zen 3 and zen 4 on a older process node.. golden cove on tsmc 5mm the gap would be 30% performance gap

 

[TESKATLIPOKA]

Golden is superior to zen 3 and zen 4 on a older process node.. golden cove on tsmc 5mm the gap would be 30% performance gap

If you think by being on a better process It will allow Intel to clock golden cove 30% harder then you should think more, way way more.

 

[itsmydamnation]

Golden is superior to zen 3 and zen 4 on a older process node.. golden cove on tsmc 5mm the gap would be 30% performance gap

Cope harder , process is going to have ~0 IPC effect.
moving to TSMC would limit the one advantage intel has when it comes to raw total single thread performance.... clock rate........

 

[SiliconFly]

talk about picking and choosing ,

So Zen 2->3,
rob 224 -> 256 , an increase of 32 entries
L1D cache 32kb -> 32kb , 0 increase
decode 4 -> 4
ALU 4 -> 4 0 increase
load 2 -> 3 ( no additional AGU or memory pipelines)
store 1->2 ( no additional AGU or memory pipelines)

skylake -> Sunny cove
rob 224 -> 352 , increase of 128 entries !!!!!!!!
L1D cache 32kb -> 48k , 50% increase
decode 3+1 -> 4+ 1 , extra decode unit
ALU 4 -> 4 0 increase
load 2 -> 2
store 1 -> 2 , 100% increase extra AGU and pipeline

Intel had to spend big in brute force adding of raw resources relative to AMD to get an equivalent level of performance increase, if you look at Zen3 AMD significantly increased utilisation of existing units by changing scheduling arrangements, sharing PRF ports and sharing of load/store ports/agu's. Now that's powder AMD still have dry and intel have spent, we will see what that powder looks like in a few months time.

Both Sunny and Golden cove aren't bad performing cores. But there not great relative to cores that spend the same level of architectural resources or get the same level of performance with significantly less spending.

Agree with the last sentence. GLC & RWC are way too fat than what they need to be. Thats why Intel is hellbent on ditching the existing fat/inefficient P-core architecture in favor of the upcoming LNC. Also, the 1st iteration of LNC makes it's debut next year. Should be exciting! (hopefully).

 

[Geddagod]

Agree with the last sentence. GLC & RWC are way too fat than what they need to be. Thats why Intel is hellbent on ditching the existing fat/inefficient P-core architecture in favor of the upcoming LNC. Also, the 1st iteration of LNC makes it's debut next year. Should be exciting! (hopefully).

LNC appears to be mega chonk as well. 8 wide decode and what, 700+ ROB? Sheesh.
Having fat archs is fine, imo, if you get the efficiency gains out of it. Wider+slower with more cache is usually supposed to be more efficient than skinny+lower latency, but GLC only just competes with Zen 3 in efficiency. I think RWC under load is going to be competitive with Zen 4 in efficiency, but if it's more efficient, then the 40% area tax they paid over Zen 4 might honestly be worth it lol.

 

[Geddagod]

talk about picking and choosing ,

So Zen 2->3,
rob 224 -> 256 , an increase of 32 entries
L1D cache 32kb -> 32kb , 0 increase
decode 4 -> 4
ALU 4 -> 4 0 increase
load 2 -> 3 ( no additional AGU or memory pipelines)
store 1->2 ( no additional AGU or memory pipelines)

skylake -> Sunny cove
rob 224 -> 352 , increase of 128 entries !!!!!!!!
L1D cache 32kb -> 48k , 50% increase
decode 3+1 -> 4+ 1 , extra decode unit
ALU 4 -> 4 0 increase
load 2 -> 2
store 1 -> 2 , 100% increase extra AGU and pipeline

Intel had to spend big in brute force adding of raw resources relative to AMD to get an equivalent level of performance increase, if you look at Zen3 AMD significantly increased utilisation of existing units by changing scheduling arrangements, sharing PRF ports and sharing of load/store ports/agu's. Now that's powder AMD still have dry and intel have spent, we will see what that powder looks like in a few months time.

Both Sunny and Golden cove aren't bad performing cores. But there not great relative to cores that spend the same level of architectural resources or get the same level of performance with significantly less spending.

I don't think GLC was that bad for what it is. Intel clearly optimized for density in their physical layout of GLC, and so despite blowing up some architectural aspects of the core, it's only (lol) 25% larger than WLC. And the ST frequency gain really was shown off with RPC (which had some in-core structure changes, but no real area increase other than from the increased L2 cache). +18% IPC, +16%/+10% ST Freq max (for RPC/GLC), and a decent increase in perf/watt to match Zen 3 isn't that bad imo. Compared to Zen 3, GLC isn't impressive, but compared to it's predecessor on Intel's side (SNC) it was fine.
SNC was just terrible because it increased area by the same or larger amount as GLC did, but GLC saw a large ST freq uplift and also nice perf/watt gains. SNC only saw the IPC uplift GLC did, and got none of the ST freq uplifts or perf/watt gains.

 

[itsmydamnation]

The challenge with attributing clock rate to a uarch when you know the process had a troubled bring up is how much of that is process , how much is layout , how much is uarch.

Zen 2,3,4 it's much easier to see given node maturity and commonality.

 

[Henry swagger]

Cope harder , process is going to have ~0 IPC effect.
moving to TSMC would limit the one advantage intel has when it comes to raw total single thread performance.... clock rate........

Lol tsmc has a density advantage and power efficiency.. intel on tsmc would slap amd around.. intel will always have leadership in single threaded performance.. you are coping 😁

 

[Henry swagger]

If you think by being on a better process It will allow Intel to clock golden cove 30% harder then you should think more, way way more.

Yes e cores would get a 30% boost easily.. tsmc has a superior node

 

[JoeRambo]

Anyone who thinks that throwing transistors ( aka having better process/packaging ) at performance does not work should see how 5800X3D or 7800X3D perform compared to vanilla variants. Same core right? 0 increase of everything right? Would not even register under what mr. @itsmydamnation listed above.

REALITY is that modern cores in "average" workload ( read not CB23 ) are completely dependant on branch prediction and memory subsystem performance. Throwing transistors at TLBs, BTBs, caches and queues works wonders for performance and guess what, it also improves efficiency, as hitting some cache is obviuosly better than going to memory and idling 500+ ROB machine.
I don't have any data, but i have seen ChipsAndCheese claim that it takes 5x more energy to go to memory instead of hitting some on chip cache and there is obviuosly large steps on where you hit, L1, L2 or L3?
So impossible to compare Zen3 that has moved to 32MB of L3 per core to WLC that was lowest point in caching that Intel is recovering to this day.

WLC is real stupid core from caching PoV as it was the first Intel core that went away from inclusive L2. Already SNC was moronic in a way 512KB L2 for 8 cores would be burning 4MB of L3 from pool to keep L2's inclusive with massive traffic and other problems.
So WLC was 1st generation product with WORST of all worlds, slow L2 cache, weak and slow L3 caching coupled with mobile levels of memory performance.

No wonder that 14nm backport of WLC did not dare to go this route and had old, inclusive 512KB L2 config, creating abomination of a product.

Intel surely can continue to throw transistors and expect good results, things can go only better if they increase L2 further, add even more L3. They are already paying that insane latency for L2 tax since WLC days, so as Raptor Lake has shown, why not reap capacity benefits.

In fact my prediction in early posts was that Intel would double dip into L2 capacity by combining two cores resources into pool of 4-6MB of L2, their latency is bad enough to allow it, so they only need to insert intermediate level of core private caches for it to shine.

 

[FangBLade]

Cope harder , process is going to have ~0 IPC effect.
moving to TSMC would limit the one advantage intel has when it comes to raw total single thread performance.... clock rate........

He's just trolling you; he knows very well that what he's writing has no connection to the truth. He does this on other forums as well; some have even banned him for it .

You were just warned on Tuesday for calling people trolls. You are filling in spaces on your ban hammer bingo card. FYI: you are not allowed to edit post containing moderator comments. - CPU mod DAPUNISHER

 

[TESKATLIPOKA]

Yes e cores would get a 30% boost easily.. tsmc has a superior node

You were talking about golden cove, but I see you did a spectacular high jump.

BTW, even E-core wouldn't achieve such boost unless they made mayor changes to It, stop continuing with this nonsense.

 

[SiliconFly]

LNC appears to be mega chonk as well. 8 wide decode and what, 700+ ROB? Sheesh.
Having fat archs is fine, imo, if you get the efficiency gains out of it. Wider+slower with more cache is usually supposed to be more efficient than skinny+lower latency, but GLC only just competes with Zen 3 in efficiency. I think RWC under load is going to be competitive with Zen 4 in efficiency, but if it's more efficient, then the 40% area tax they paid over Zen 4 might honestly be worth it lol.

Actually, MTL SoC will surely be much more power-efficient than a Zen 4 cpu. But I don't think a single RWC P-core will be more power-efficient than a single Zen 4 core. Not even close I think (in spite of being on Intel 4).

I like Intel a lot. But frankly speaking, I think RWC has reached evolutionary dead end. Time to rhrow it out. And time for LNC to take over.

 

[AMDK11]

talk about picking and choosing ,

So Zen 2->3,
rob 224 -> 256 , an increase of 32 entries
L1D cache 32kb -> 32kb , 0 increase
decode 4 -> 4
ALU 4 -> 4 0 increase
load 2 -> 3 ( no additional AGU or memory pipelines)
store 1->2 ( no additional AGU or memory pipelines)

skylake -> Sunny cove
rob 224 -> 352 , increase of 128 entries !!!!!!!!
L1D cache 32kb -> 48k , 50% increase
decode 3+1 -> 4+ 1 , extra decode unit
ALU 4 -> 4 0 increase
load 2 -> 2
store 1 -> 2 , 100% increase extra AGU and pipeline

Intel had to spend big in brute force adding of raw resources relative to AMD to get an equivalent level of performance increase, if you look at Zen3 AMD significantly increased utilisation of existing units by changing scheduling arrangements, sharing PRF ports and sharing of load/store ports/agu's. Now that's powder AMD still have dry and intel have spent, we will see what that powder looks like in a few months time.

Both Sunny and Golden cove aren't bad performing cores. But there not great relative to cores that spend the same level of architectural resources or get the same level of performance with significantly less spending.

You are right.AMD is clearly using better resource management algorithms, better prefetching and predictor.As far as I know, AMD does simulations before implementing the architecture on silicon.Intel did samples before correcting the design bugs.AMD's method is faster.I heard that Intel will also simulate the microarchitecture before producing the samples.We'll see.

The analogy is with cars: Intel uses the brute force of the amount of resources like American cars with large engine capacities without turbo, and AMD uses the brute force of optimization and better algorithms like European turbo engines to squeeze more from the same amount of resources.Maybe LionCove is a change of approach?

 

[Geddagod]

Anyone who thinks that throwing transistors ( aka having better process/packaging ) at performance does not work should see how 5800X3D or 7800X3D perform compared to vanilla variants. Same core right? 0 increase of everything right? Would not even register under what mr. @itsmydamnation listed above.

This is hilariously disingenuous lmao. If you think 3D stacking SRAM is just "throwing transistors" at the problem... ok buddy. Regardless, I think it was pretty clear it was in reference to core structure sizes, not necessarily just cache sizes. I've referenced to GLC's strong private L2 caches before, I have no beef with that.
Btw throwing transistors at the problem isn't "aka having better process/packaging". Where did you get that idea?

REALITY is that modern cores in "average" workload ( read not CB23 ) are completely dependant on branch prediction and memory subsystem performance. Throwing transistors at TLBs, BTBs, caches and queues works wonders for performance and guess what, it also improves efficiency, as hitting some cache is obviuosly better than going to memory and idling 500+ ROB machine.
I don't have any data, but i have seen ChipsAndCheese claim that it takes 5x more energy to go to memory instead of hitting some on chip cache and there is obviuosly large steps on where you hit, L1, L2 or L3?
So impossible to compare Zen3 that has moved to 32MB of L3 per core to WLC that was lowest point in caching that Intel is recovering to this day.

Ye I'm calling "poop" (don't ban me mods lol) on that argument. Both CBR20 and CBR23 report 19-20% IPC uplifts, so they are obviously taking advantage of the cores bigger resources. Ironically, your "WLC/SNC has a weaker memory subsystem than Zen 3 so it can't be compared" argument applies less in consideration with CB than in real world workloads, meaning that if you want to isolate the "core" for itself, CB is one of the better applications to do it with.
But even if you have a hate CB, SNC's worse power efficiency has shown itself in other benchmarks such as handbrake or x264 encoding... vs SKL.

Intel surely can continue to throw transistors and expect good results, things can go only better if they increase L2 further, add even more L3. They are already paying that insane latency for L2 tax since WLC days, so as Raptor Lake has shown, why not reap capacity benefits.

If they can get the efficiency benefits out of it, then the area tax might be worth it. Problem is that Intel doesn't see perf/watt benefits out of it. GLC is just as efficient as Zen 3, despite having massively larger core resources and L2.

 

[eek2121]

Really? Tell me one existing Ryzen mobile chip that has a GPU that's even half as good as MTL's.

All of them. There are still games that CTD on Intel GPUs to this day due to driver issues. Intel has gotten better, but they are still trailing AMD.

Lol tsmc has a density advantage and power efficiency.. intel on tsmc would slap amd around.. intel will always have leadership in single threaded performance.. you are coping 😁

Incorrect except somewhat regarding that first part.

Actually, MTL SoC will surely be much more power-efficient than a Zen 4 cpu. But I don't think a single RWC P-core will be more power-efficient than a single Zen 4 core. Not even close I think (in spite of being on Intel 4).

I like Intel a lot. But frankly speaking, I think RWC has reached evolutionary dead end. Time to rhrow it out. And time for LNC to take over.

That id going to depend on how much Intel has overclocked/pushed the chips outside of their sweet spot. Intel took a 28W “P” chip and rebadged it as a 45-55W “H” chip. Efficiency will suffer as s result.

PS Tiger Lake was Intel’s Zen 3.

 

[JoeRambo]

Ye I'm calling "poop" (don't ban me mods lol) on that argument. Both CBR20 and CBR23 report 19-20% IPC uplifts, so they are obviously taking advantage of the cores bigger resources. Ironically, your "WLC/SNC has a weaker memory subsystem than Zen 3 so it can't be compared" argument applies less in consideration with CB than in real world workloads, meaning that if you want to isolate the "core" for itself, CB is one of the better applications to do it with.
But even if you have a hate CB, SNC's worse power efficiency has shown itself in other benchmarks such as handbrake or x264 encoding... vs SKL.

What? So you are somehow taking my argument that excludes CB23 ( cause it performed real good due to not leaving core ) and somehow make it Yours. Sorry i don't follow the rest, makes no sense. But i just hope that You do understand that You can't discuss power efficiency without V/F curve and process characteristics. And 10nm variant of SNC's was not exactly known for good things here. And ironically this loops back to origins of discussion about process.

PS Tiger Lake was Intel’s Zen 3.

Yup, they just needed a proper desktop chip with good clocks and decent process characteristics.

 

[Geddagod]

What? So you are somehow taking my argument that excludes CB23 ( cause it performed real good due to not leaving core ) and somehow make it Yours.

Oh are you saying CB R20 and CB R23 are an overestimate of core IPC then because it doesn't account for the memory subsystem/branch prediction? At that point, I would argue that a)Stuff like L3 and IMC aren't really being counted as the "cores" advantage but SOC/interconnect design, and b)AMD's BPU is at the very least, still as good as GLC, as shown by chips and cheese testing in "non cinebench" workloads such as 7zip and libx264 (showing the branch prediction accuracy of AMD).
Besides, I still don't see exactly how your arguing that CB isn't a "real" workload when it closely averages the perf seen in other benches as well (such as gaming averages).

But i just hope that You do understand that You can't discuss power efficiency without V/F curve and process characteristics. And 10nm variant of SNC's was not exactly known for good things here.

Again, even assuming 10nm+ didn't improve efficiency at all over 14nm+++, SNC doesn't have more perf/watt than CML. And ye, 10nm+ isn't known to scale to high power, but I'm talking about 15 watt mobile parts in mobile over here.
And if you want to compare high power as well, rocket lake vs comet lake shows that SNC isn't impressive either, since cypress cove is esentially backported sunny cove.
Over here, you see that under the 65 watt power limit for the 10400f vs 11400f (POV ray) comet lake boosts ~12% faster than rocket lake. Which means you get ~5% better perf/watt in applications that can take advantage of the on average 18% IPC.
However, I will add that at that power range, we are looking at a total of ~11 watts per core +fabric, which is pretty much only useful in desktop, and not the much more profitable and important mobile and server power ranges.
This is in comparison to Zen 3, which increased frequency iso power across all power levels and thus resulted in a 15-20% perf/watt improvement across all power levels. And it also increased area less than SNC did as well. Hard to argue Intel's "moar transistors" strategy is working well, is it?

PS Tiger Lake was Intel’s Zen 3.

Tiger Lake was Intel's worse Zen 3. Higher power consumption iso perf.

 

[H433x0n]

You are right.AMD is clearly using better resource management algorithms, better prefetching and predictor.As far as I know, AMD does simulations before implementing the architecture on silicon.Intel did samples before correcting the design bugs.AMD's method is faster.I heard that Intel will also simulate the microarchitecture before producing the samples.We'll see.

The analogy is with cars: Intel uses the brute force of the amount of resources like American cars with large engine capacities without turbo, and AMD uses the brute force of optimization and better algorithms like European turbo engines to squeeze more from the same amount of resources.Maybe LionCove is a change of approach?

They both simulate their micro architectures.

The difference is way simpler than you think - AMD fundamentally sells a single product. They’ve got way more manpower and resources dedicated to creating that single CCD that is shared across the entire lineup of Ryzen and Epyc processors. It’s all just playing legos. The periphery technologies such as PCIE 5, DDR5 PHY & Chipsets? Those are out sourced. Their engineering talent is hyper focused and not scattered across dozens of responsibilities (despite having much less staff overall).

They’ve now got the Zen 4C ccd but even then, we’re talking about only 2 core products.

 

[yuri69]

The difference is way simpler than you think - AMD fundamentally sells a single product. They’ve got way more manpower and resources dedicated to creating that single CCD that is shared across the entire lineup of Ryzen and Epyc processors. It’s all just playing legos. The periphery technologies such as PCIE 5, DDR5 PHY & Chipsets? Those are out sourced. Their engineering talent is hyper focused and not scattered across dozens of responsibilities (despite having much less staff overall).

In 2022 Intel got 132k employees compared to AMD's 25k. In theory, Intel can afford having over 5 "AMD-sized" projects. Also Intel still can afford the top talent.

Intel runs multiple core IP teams with their over 5 times AMD headcount...

 

[Glo.]

In 2022 Intel got 132k employees compared to AMD's 25k. In theory, Intel can afford having over 5 "AMD-sized" projects. Also Intel still can afford the top talent.

Intel runs multiple core IP teams with their over 5 times AMD headcount...

Intel has more software engineers than AMD and Nvidia have engineers combined. Total.

 

[Ajay]

In 2022 Intel got 132k employees compared to AMD's 25k. In theory, Intel can afford having over 5 "AMD-sized" projects. Also Intel still can afford the top talent.

Intel runs multiple core IP teams with their over 5 times AMD headcount...

AMD doesn't have any more difficulty recruiting top talent than any other top semiconductor design company. The sheer size of Intel makes turning that 'ship' in the right direction a much more lengthy process than the rather nimble AMD. AMD pulled off a 180 with Zen with surprising speed, in part, because of the smaller size of their teams and lower burden of corporate accountability (aka bureaucracy)

I wonder how much the FAB side of the business was slimmed down - because they seem to have some real momentum there. I know that some top people, with storied careers were either encouraged to move on or retire.

 

[Abwx]

In 2022 Intel got 132k employees compared to AMD's 25k. In theory, Intel can afford having over 5 "AMD-sized" projects. Also Intel still can afford the top talent.

Intel runs multiple core IP teams with their over 5 times AMD headcount...

You have to account for the manufacturing part that work in process issues, a better comparison would be the revenue ratio wich is 3, so three time rather than 5x.

 

[H433x0n]

In 2022 Intel got 132k employees compared to AMD's 25k. In theory, Intel can afford having over 5 "AMD-sized" projects. Also Intel still can afford the top talent.

Intel runs multiple core IP teams with their over 5 times AMD headcount...

This isn’t a slight against AMD. They revolutionized resource efficiency. They’ve got a lot less to worry about by design.

Intel runs a foundry, they develop their own networking, critical IP such as memory PHY, PCIe, chipsets are developed in-house and until recently relied on internal EDA tools. They perform the functions of multiple companies (AMD, TSMC, Synopsis, Asmedia, etc).