Does thermal expansion of such a large die also have the potential to limit sizes?
Yes and no (

did you honestly expect any less of an answer?

)
Thermal expansion plays havoc with many different aspects of the engineering and electrical performance (including reliability over time) of the chip.
And the larger the chip, the more of an issue that becomes from a "pin shear stress" perspective. (
see slide 16)
However, in my efforts to be brief for the sake of maintaining a legible and digestible response, my concern here is that my words will leave you with the impression that it is more of a concern than it really is.
Suffice to say, yes it is something that is of large enough consequence that it requires the engineers to factor it in, but at the same time it is small enough of an absolute impact that I can't think of a specific example where it has ever limited the die size of an IC or circuit.
Not to date myself, but eons ago when I worked with SUN Sparc chips the die sizes were considerable and film delamination from thermal mismatch really was a problem. But, in restrospect, the truth of the matter was that at the time a lot of us engineers (myself included!) on that project were just ignorant (or naive) of the issues and it was simply a matter of gaining experience (which we did!) in handling silly things such as dummy fill patterns and metal density requirements to design-in some counter stresses for the whole thermal mismatch situation.
What it really boils down to is that, as a materials science engineer, you have to approach an integrated circuit as if it were a composite material for which you must balance thermal mismatch as a straightforward linear process of adjusting the relative weighting ratios of your admixtures of each component present in the composite. X amount of copper, Y amount of methylated silicon oxide, Z amount of silicon substrate, etc., etc.
Not to understate or overstate the severity of the situation, but suffice to say it is not a problem until such time that it becomes one
That on die fabric is getting seriously complex! The "cluster on die" mode is pretty interesting- just treat the two rings as separate NUMA nodes, except with extremely high speed on-chip switches between them instead of off-die QPI links.
I wonder where the fabric design will go next? Will they go back to a single, larger bidirectional ring? More "clusters" of cores on their own rings, connected in a network by switches? Or something more like Knights Landing's 2D-mesh fabric?
It really is, and yet in some ways it seems needlessly so. This is a 3D problem that has been resolved via a 2D engineering solution which results in some quirky one-off solutions IMO.
Not that I am questioning Intel's engineering decisions, they have surely ran the design through an order of 10^6 more simulated performance scenarios than I have in my wee little mind, so all I can pontificate on are the academic solutions that can be concocted without the restraint of the chip being economically viable
Which leads to Intel17's excellent observation and point:
What a solid piece of engineering.
^ to which I say "+1"