That die is massive... Imagine a GPU that big on that process.. I wish Intel would make GPUs. Is it a safe assumption no one else is capable of producing anything like that ?
Die size is reticle (litho) limited in a hardware sense. Any fab with the same litho tools (same hardware-limited reticle size) could/can produce a wafer with dies the same size as Intel.
That is the trivial/academic answer to your question, but I suspect you meant to ask a slightly different question.
Rather, I suspect you meant to ask if it was safe to assume no one else is capable of yielding chips of that size while managing to have the performance/capabilities of those chips be such that the chips can command the price-point necessary for the company to make sufficiently large enough profits once the costs of the chip (which includes yields, both functional and parametric) were appropriately accounted for...to which I would answer with a strong "YES!"
To have a chip be as large as the 2699V3, yielding in high enough quantities for the binned SKU (both functional and parametric), while simultaneously providing enough performance and value-add such that the end-user is willing to pony up the dosh to pay for it (and thus make it worth Intel's time developing and producing) is a feat that pretty much no one else can approach (save for possibly IBM, but that is a situation where the economic picture of their large-die SKUs is perhaps obfuscated by their integrated hardware/software/service contract sales model).
Those are massive dies.
Can someone explain why they use areas of the wafer that clearly cannot yield a usable chip?
Partial dies along the edge of the wafer are still printed and etched as key means of decreasing functional yield loss for the rest of the wafer.
A lot of particles are generated from film delamination along the edge of the wafer. If you don't pattern and etch those partial die along the perimeter of the wafer then the thicknesses of the film stacks along the edge of the wafer become asymmetric with respect to the areas that are being patterned and etched as full die. A big issue when you go to CMP.
Much easier to just pattern and fill those partial dies, eliminating proximity effects and fill effects, for the neighboring dies that you do want to sell.
It isn't necessary, you can do blanket field/shot exposure (or not) on those partial dies if you desired. But you'll take a yield hit from the associated rise in defectivity across the rest of the wafer when those partial dies become defect generators at later stages of processing.
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