Intel is going to integrate Memory controllers on Server chips...

[Viditor]

Originally posted by: stevty2889

Originally posted by: clarkey01

Originally posted by: stevty2889
65nm isn't in full production yet, but will be ramping up shortly.

Q4

We are closer to ramping up than that, probably the begining of next month.

They build up a stock pile before they release the chips, so production begins usualy 6 months or more before they are released..

There are a couple of reasons why I am dubious of this claim stevty...

1. At 65nm on 300mm, Intel should require only one full turn for buildup (3 months), even for the quantities they are expecting to ship...
2. Ramping usually happens as samples are sent out to the OEMs for system design, and either security is tighter on this than ever before or it hasn't happened yet...

 

[Duvie]

Originally posted by: Intelia
Rambus is tring to get back with Intel Man I hope its going tobe XDR I well go get the link and post it . Did anyone else read that report at the inquire 2 weeks ago I looked can't find the thread Hay Itanic ondie memory controLLer Maybe Apple O/S for Itanic All 1 year ahead of my time frame. Pinch me Iam dreaming. Apple servers ??? Remind me to never get Intel angry. 65 nano tech less leakage than antisapated I have never seen David so gidi in my life. He wants it to be XDR so bad. 8mb catch oh oh oh this is so cool. I have to go see Zinn2b's post . I know he's going nuts. Guys not tring to be smart arse but zinn is looking like a genious . I know he is seeing $$$$$ signs. I go check him out.
More breaking news Zinn has backed off he is just so pleased how everything has turned out . He seems to be at peace with himself. Good for him . Gee it just gets better and better

What the heck does David know about this?? Short of a handful of ppl at Ronler acres in Hillsboro,OR this information is not spread about and known for sure...

remember the great reports we got from 90nm switch from Intel to get the Prescot....




Also to all the Intel fans...Why is it when ppl talk about Intels future they alwys seem to think AMD will be in suspended animation?? Like amd wont evolve....They came with 90nm quite a bit later then Intel but really didn't need it...130nm FX55s were doing 2.6ghz with reasonable heat....90nm was obviously the break point for making dual cores cost effective and to help reduce the thermals....That being said I dont think they need 65nm as fast as Intel does. Theyu can go with this continual process a bit longer and hopefully switch with the first sockt M2 offering....


As for Intel copying yet again another AMD idea in its architecture....NOT SURPRISED!!! AMD may have done it in the past but what ppl need to remember in the tech world it is not what you have don in the past but what you have done lately that counts......

 

[Viditor]

Clock speeds on pressler are only speculative now. Even people working at intel cant tell what pressler yields will be in 6 months.

A 3.8 northwood core would not be much faster than a 3.8 prescott core (this has been tested).

the pipeline has nothing to do with the process technology, i dont understand why you associated 65nm with shortening the pipeline.

All signs point to pressler sucking pretty much, the same margainal gains we got from prescott repeated.

Yonah and Meram are the cpus to watch.

Well, I'm not sure I agree with all of this...
1. I feel sure that a number of engineering samples have already been produced, which would give Intel a very good idea on what bin speeds to expect (though not the yields, as you say).
2. The pipeline CAN be associated with the process technology if you think of it as a solution to the heat. It will depend on how well the 65nm process does...
3. I tend to agree that Presler dual core won't be anywhere near up to AMD standards
4. I doubt that Yonah will be anywhere near as exciting as Merom or Conroe. But even Merom/Conroe will need a new platform with CSI to start hitting their potential, and that's not due until 2007...

 

[Viditor]

Intel on the yonah 2mds of shared catch Merom 4 mds of shared catch/ Everone is saying the presslers(preslers I have seen it spelled both ways LOL) Are going to be just a shrunk P4P but I did read where they added some things to it from Dothan Fusion engine and shorter pipes . I have looked everywhere for that info can't find. Oh well. In Anands latest Intel road maps Anand states its 65nano P4P but latter he says it doesn't appear that they shortened the pipes . Which tells me that Anand might have heard the same as me but it doesn't appear by the high clock speeds that the pipes were shortened 3.8 is the highest. Is it possiable (please imput your thoughts) that they could be using a northwood die . 3.8 north would be a strong performer. Part I am confused by is 90nano goes to 3.8 I would think 65nano go to 4.2 at least. Your imput please and lets play nice.

Some things to remember here...

1. Just to get 2 Cedarmill cores on one die means they have to reduce heat drastically. So not increasing the clockspeed and not shortening the pipelines should come as no surprise. I think the estimates of 2.8 - 3.4 GHz for Presler sound about right...
2. Presler is HUGE for a 65nm chip (140mm2) which is probably due to the 4mb of cache. The biggest advantage for Intel is that 65nm allows more chips per wafer making each one less expensive to produce, however the doubled cache negates quite a bit of that.
3. Doubling the cache hasn't worked very well for performance in the past on the Netburst chips...if it follows the same pattern as the last time, we should see performance gains in the low double or high single digits.
4. Intel's major bottleneck is no longer memory channels, but it's the FSB. Until they finish developing CSI, it will probably remain so. They are doing what they can as a way to patch it up (increasing the FSB speed, creating dual FSBs), but these temporary solutions have their limitations as well. CSI (for those who don't know) is very similar to AMD's HT, except that it is a ring design rather than a point-to-point design. This will help the Intel platform better distribute the data and avoid the FSB bottleneck. AMD obviously doesn't have this problem as they have HT already and there is no central bus to tie things up...

 

[stevty2889]

Originally posted by: Viditor

Originally posted by: stevty2889

Originally posted by: clarkey01

Originally posted by: stevty2889
65nm isn't in full production yet, but will be ramping up shortly.

Q4

We are closer to ramping up than that, probably the begining of next month.

They build up a stock pile before they release the chips, so production begins usualy 6 months or more before they are released..

There are a couple of reasons why I am dubious of this claim stevty...

1. At 65nm on 300mm, Intel should require only one full turn for buildup (3 months), even for the quantities they are expecting to ship...
2. Ramping usually happens as samples are sent out to the OEMs for system design, and either security is tighter on this than ever before or it hasn't happened yet...

DID will start ramping next month, the other 2 65nm fabs will be ramping later. We won't be instantly going to full production, thats why it's called ramping up..it will be around 3 months before D1D goes to full production. They have working samples of yonah and cedar mill, not sure how many, or what clock speeds they are getting though.
Presler isn't really a single die, it's just like smithfield, it's 2 seperate cedar mill die in a single package, while yonah is a true dual core with shared cache. And merom looks like it may come out sooner than expected.

 

[Viditor]

Originally posted by: stevty2889



DID will start ramping next month, the other 2 65nm fabs will be ramping later. We won't be instantly going to full production, thats why it's called ramping up..it will be around 3 months before D1D goes to full production. They have working samples of yonah and cedar mill, not sure how many, or what clock speeds they are getting though.
Presler isn't really a single die, it's just like smithfield, it's 2 seperate cedar mill die in a single package, while yonah is a true dual core with shared cache. And merom looks like it may come out sooner than expected.

I do understand ramping...
At 140mm2 on 300mm wafers, that's ~ 450 candidate dice per wafer. Correct me if I'm wrong, but D1D has a 5000 wspm capacity, so that if we assume a 20% production (and I would hope that it ramps a little faster than that...), that's 450,000 candidate chips/month...
If yields are even 33%, that's 1 million+ chips in time for launch!
As Intel is only expecting to sell about that many of the 820D line over the next 6 months, why would they need such a large buildup for a launch that's taking place AFTER Xmas??

 

[stevty2889]

D1D won't ramp to 5000 wafer starts, we are starting at 500, and then ramping up over 3 months to 2500 wafer starts. We are sharing the fab with development, so part of the capacity goes them. The other two 65nm fabs will ramp to their full capacity, but not until closer to the end of the year.

 

[Viditor]

Originally posted by: stevty2889
D1D won't ramp to 5000 wafer starts, we are starting at 500, and then ramping up over 3 months to 2500 wafer starts. We are sharing the fab with development, so part of the capacity goes them. The other two 65nm fabs will ramp to their full capacity, but not until closer to the end of the year.

That's about what I figured...I actually was saying that the capacity was 5000 wspm, but the 20% I mentioned comes to 1000 wspm. Assuming a linear ramp (not a good assumption, but I don't have data to make a better one...) and a 40% yield, that means you should have ~800,000 finished CPUs by the beginning of next year...that sure seems like a lot!

 

[pm]

Originally posted by: Sixtyfour
But seriously, it's IBM that has excellent 65nm process that has much less leakage.

Do you have any numbers to back up that claim? Much less leakage than what? Intel?

I agree that they have an excellent 65nm process. That almost goes without saying, but "has much less leakage" implies that you have comparison data.

Could you point me to some links - or even journal or proceedings that compare the two processes? Are you comparing the LP process presented at the 2004 IEDM? And what Vt levels are you using to compare? HVT?

Originally posted by: Viditor
That's about what I figured...I actually was saying that the capacity was 5000 wspm, but the 20% I mentioned comes to 1000 wspm. Assuming a linear ramp (not a good assumption, but I don't have data to make a better one...) and a 40% yield, that means you should have ~800,000 finished CPUs by the beginning of next year...that sure seems like a lot!

I know a fair bit about process technology at a low level, but not a lot about fab throughput. WSPM? My guess is "Wafer Starts Per Month"? Is that right?

 

[Viditor]

Originally posted by: pm
I know a fair bit about process technology at a low level, but not a lot about fab throughput. WSPM? My guess is "Wafer Starts Per Month"? Is that right?

Correct. Maybe some other common Fab terms would be helpful as well...

A "turn" = the period it takes to go from a raw wafer to a completed one (usually about 90 days)
WSPW = obvious
Dice = the finished pieces of the wafer that are assembled into the chip when it's "cut up"
Packaging = assembling the dice into a chip
APM = Automated Precision Manufacturing...used by AMD to automatically tweak production in realtime. It can change what the product will be in the middle of production, and automatically tweaks the production of each wafer.
"Copy Everything" = Intel's method of production. Once they have a Fab tweaked properly, they "copy everything" into the next Fab, thus reducing the learning curve to a very low level. This is one reason Intel's Fabs are much smaller than AMD's (Fab 30 has a capacity of 5,500 wspw, D1D has a capacity of 5,000 wspm)

 

[pm]

Thanks, Viditor/Charles.

 

[Sentential]

Originally posted by: Viditor

Intel on the yonah 2mds of shared catch Merom 4 mds of shared catch/ Everone is saying the presslers(preslers I have seen it spelled both ways LOL) Are going to be just a shrunk P4P but I did read where they added some things to it from Dothan Fusion engine and shorter pipes . I have looked everywhere for that info can't find. Oh well. In Anands latest Intel road maps Anand states its 65nano P4P but latter he says it doesn't appear that they shortened the pipes . Which tells me that Anand might have heard the same as me but it doesn't appear by the high clock speeds that the pipes were shortened 3.8 is the highest. Is it possiable (please imput your thoughts) that they could be using a northwood die . 3.8 north would be a strong performer. Part I am confused by is 90nano goes to 3.8 I would think 65nano go to 4.2 at least. Your imput please and lets play nice.

Some things to remember here...

1. Just to get 2 Cedarmill cores on one die means they have to reduce heat drastically. So not increasing the clockspeed and not shortening the pipelines should come as no surprise. I think the estimates of 2.8 - 3.4 GHz for Presler sound about right...
2. Presler is HUGE for a 65nm chip (140mm2) which is probably due to the 4mb of cache. The biggest advantage for Intel is that 65nm allows more chips per wafer making each one less expensive to produce, however the doubled cache negates quite a bit of that.
3. Doubling the cache hasn't worked very well for performance in the past on the Netburst chips...if it follows the same pattern as the last time, we should see performance gains in the low double or high single digits.
4. Intel's major bottleneck is no longer memory channels, but it's the FSB. Until they finish developing CSI, it will probably remain so. They are doing what they can as a way to patch it up (increasing the FSB speed, creating dual FSBs), but these temporary solutions have their limitations as well. CSI (for those who don't know) is very similar to AMD's HT, except that it is a ring design rather than a point-to-point design. This will help the Intel platform better distribute the data and avoid the FSB bottleneck. AMD obviously doesn't have this problem as they have HT already and there is no central bus to tie things up...

Thankyou very much for that post. I honestally do not know much about Intel's CSI model but it looks quite interesting to say the least.

Question(s) for those who are in the know and are able to release said infomation:

#1 Will Presler have 1066 FSB on all models?
#2 Hyperthreading...Which core(s) are going to get it? Or both?

Thats the only real factor for me at this point in time. If Presler has either 266 or HT it would be worth while to pay the premium for it. However if they do not and only Cedar Mill has HT I might stick with that route.

 

[Viditor]

The latest info I have is that Presler will be 800MHz FSB...but I am not an authority.

 

[Sentential]

Originally posted by: Viditor
The latest info I have is that Presler will be 800MHz FSB...but I am not an authority.

Gotcha. Frankly Im more worried about HT. If Presler is an identical carbon copy of Smithfield then I will stick with Cedar Mill

 

[Viditor]

Let me add just a few thoughts...
It's quite obvious that AMD pretty much has a lock on being superior on all products this year except mobile. They also probably have a lock already on next year as well, and they stand a good chance of picking up significantly next year in mobile...

That said, 2007 may very well be The Revenge of the Sith (or Jedi, depending on your POV).
In 2007, Intel will be releasing:
1. CSI...you all should research that!
2. Whitefield...combining Itanium and Xeon into a single platform
3. Expansion and refinement of the Merom/Conroe chips (Yonah based 64bit desktops)
4. Rumours abound that Intel's High-K process has been dropped, which begs the question of what they plan to use instead for 45nm?

Meanwhile (as Duvie has pointed out), AMD will NOT be standing still...
1. In 2006 the Socket F may have much more of an impact than people expect because of FB-DIMM
2. There will be another HT speed increase next year
3. Quad cores in 2007

All in all, 2007 is shaping up to be one HELL of a year for all computer systems.

BTW...the reason I mentioned all of this is that if you're anything like me, you tend to turn over your computer system about every 2 years. If that IS the case, then don't wait TOO long to make that upgrade. The reason being that in 2007, no matter WHICH company you prefer, you are gonna be drooling for a new one!

 

[Sentential]

Yea its starting to sound like the early 90s all over again. Damn shame the stock market doesnt pick back up again

 

[Viditor]

Originally posted by: Sentential
Yea its starting to sound like the early 90s all over again. Damn shame the stock market doesnt pick back up again

Patience...we just had the worst recession since the Great Depression. It should take a good 3 years to uptick at a strong level.
BTW, analysts are now predicting that the S&P 500 should hit an all-time record high sometime next year...

 

[Intelia]

Originally posted by: stevty2889

Originally posted by: Viditor

Originally posted by: stevty2889

Originally posted by: clarkey01

Originally posted by: stevty2889
65nm isn't in full production yet, but will be ramping up shortly.

Q4

We are closer to ramping up than that, probably the begining of next month.

They build up a stock pile before they release the chips, so production begins usualy 6 months or more before they are released..

There are a couple of reasons why I am dubious of this claim stevty...

1. At 65nm on 300mm, Intel should require only one full turn for buildup (3 months), even for the quantities they are expecting to ship...
2. Ramping usually happens as samples are sent out to the OEMs for system design, and either security is tighter on this than ever before or it hasn't happened yet...

DID will start ramping next month, the other 2 65nm fabs will be ramping later. We won't be instantly going to full production, thats why it's called ramping up..it will be around 3 months before D1D goes to full production. They have working samples of yonah and cedar mill, not sure how many, or what clock speeds they are getting though.
Presler isn't really a single die, it's just like smithfield, it's 2 seperate cedar mill die in a single package, while yonah is a true dual core with shared cache. And merom looks like it may come out sooner than expected.

Nice post can you say more on merom I heard 2qt/06

 

[stevty2889]

Originally posted by: Sentential

Originally posted by: Viditor
The latest info I have is that Presler will be 800MHz FSB...but I am not an authority.

Gotcha. Frankly Im more worried about HT. If Presler is an identical carbon copy of Smithfield then I will stick with Cedar Mill

As far as I know, cedar mill and presler will both run on 800mhz FSB. Presler is just two cedar mill die in one package, the same as smithfiled(the current dual cores) is just 2 prescotts in one package. Don't know about hyperthreading though, they don't give us many details, guess they don't want the info getting out.

 

[Acanthus]

What i dont get is if DFI, Asus, and Abit can get boards that run at 1200fsb out of current chipsets, what the hell is stopping Intel from officially supporting it? FSB is a heavy bottleneck in dual core CPUs and they would certainly benefit from the increase.

 

[Viditor]

Originally posted by: Acanthus
What i dont get is if DFI, Asus, and Abit can get boards that run at 1200fsb out of current chipsets, what the hell is stopping Intel from officially supporting it? FSB is a heavy bottleneck in dual core CPUs and they would certainly benefit from the increase.

Because Intel must attain a higher standard than the mobo makers. While the MM can attain those speeds and be stable a good portion of the time, Intel must be stable 100% of the time or they will be issuing recalls pretty quickly...

 

[Viditor]

Originally posted by: Intelia
Nice post can you say more on merom I heard 2qt/06

I believe Merom is set for Q4 06...that is moved up drastically from their original 2007-8 timeframe...
The CSI platform for Merom is still set for the 2007 timeframe, so we will probably see 2 versions of Merom.

 

[Acanthus]

Originally posted by: Viditor

Originally posted by: Acanthus
What i dont get is if DFI, Asus, and Abit can get boards that run at 1200fsb out of current chipsets, what the hell is stopping Intel from officially supporting it? FSB is a heavy bottleneck in dual core CPUs and they would certainly benefit from the increase.

Because Intel must attain a higher standard than the mobo makers. While the MM can attain those speeds and be stable a good portion of the time, Intel must be stable 100% of the time or they will be issuing recalls pretty quickly...

Im just saying that if the mobo makers can do it with intels old chipsets (hell as old as I875) i dont see any reason why they cant do itnow, on newer process technology. Hell, just give us dual core with 1066fsb at least, theyll actually use it, unlike the EE.

 

[Intelia]

Originally posted by: Viditor

Originally posted by: Intelia
Nice post can you say more on merom I heard 2qt/06

I believe Merom is set for Q4 06...that is moved up drastically from their original 2007-8 timeframe...
The CSI platform for Merom is still set for the 2007 timeframe, so we will probably see 2 versions of Merom.

More Info More Info keep it coming

 

[clarkey01]

Intel does have a point to point bus in the works.