That expectation seems a bit sketchy. First of all Sandy/Ivy Bridge doesn't have a trace cache but a uop cache, and going back to a NetBurst-style trace cache for Haswell is extremely unlikely.
Even if we assume they meant an L2 uop cache, it still doesn't make a whole lot of sense. Uops are relatively big, and the purpose of the uop cache is to lower the branch misprediction latency and save on decoding power. Missing the L1 uop cache and having to access an L2 uop cache adds latency, so there's probably no gain there. And the L1 uop cache already has a hit rate of 80% so an L2 uop cache wouldn't significantly lower the decoder activity either. Besides, the uop cache is really more like an L0 instruction cache. So I don't see where another cache level would fit in.
The only thing I can imagine is that the L1 instruction cache would contain predecoding information. It would lower the branch misprediction latency by a bit and potentially save some power. More importantly this could also allow them to perform macro-op fusion between a mov and an arithmetic instruction. The predecoder could check for operand dependencies in a power efficient way since it wouldn't be pressed for time if it sits between the L2 and L1 cache. It also saves uop cache space since they are non-destructive already.
This would improve Haswell's scalar IPC by several percent.
