DrMrLordX
Lifer
I could see Xe on 7nm in late 2021. That's Intel's pipecleaner for the node, just like Vega20 was AMD's pipecleaner for all their 7nm products from TSMC.
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I could see Xe on 7nm in late 2021. That's Intel's pipecleaner for the node, just like Vega20 was AMD's pipecleaner for all their 7nm products from TSMC.
IntelUser2000
Elite Member
Yes, and while its easy to expect they'll continue to screw up, the old guard is gone and they are being more careful with 7nm. Both 14nm and 7nm delays are due to doing more than they could handle.
If we do get 70 TFlops for the Ponte Vecchio product, that means each chip can deliver ~4.5 TFlops. And that's in actual performance, so peak might be 5 TFlops, in FP64.
On top of that, they need to put the Foveros layer on the bottom working, and EMIB for the HBM, and put 16 of those 5 TFlop chips on it. It may be a "pipe-cleaner" but not a easy one at all.
I get it, that is technically not impossible, but it reminds me when people believed so hard all through 2016 that Vega will eventually be launched that year. That too was beyond the limits of optimism for me. I can see functioning 7nm silicon in some form coming back to the labs even next year, but to ship enough actual Sapphire Rapids CPUs and enough of these very ambitious Xe chips to bild an Exaflop+ supercomputer in 2021? All I'm saying is, I'm not holding my breath.
Just as a side note, yes, for sentimental reasons and out of a sense of fairness, I'm quite pro AMD for many years now even though I own a PC with an Intel CPU and an NVIDIA card 🙂 - but I find the announced product very-very compelling, and I really don't want to see it fail 🙂
That doesn't even sound ambitious from Intel, that's borderline delusional. I see it just as realistic as was their 5G modem. Almost everybody knew it wasn't happening, but they kept announcing it over and over. Even a couple of weeks before officially bailing out, they have just kept saying it, and showing 'something' that looked like an 5G modem, all the while they never had a functioning and actually mass producible chip... I hope this Ponte Vecchio will be different, because it looks juicy 🙂
Aurora is pretty much going to be fabbed at "risk production" levels and the chiplets do seem pretty small. And remember it takes time to get everything assembled and setup. So actually fabbing the chips in late 2020 still seems realistic although you won't see any other products on Intel's 7 nm node for some time.
zinfamous
No Lifer
"The Old Bridge" ....doesn't really have the punch one is used to in this industry. 😀
Yes, I know what they are specifically referring to...but maybe an odd icon to pin your name on, because that name is a bit like Chevy trying to sell their "No Go" in Mexico back in the 70s 😀
That’s odd. A Nvidia V100 SMX2 has a target power consumption of 300W. V100 is a big GPU. I think we are expecting multiple chiplets for the Xe HPC card, so power consumption could scale more easily. Still, I wonder if these GPUs are really power inefficient. There are other power sinks in the system like memory, storage and a lot of interconnect power. The numbers could be off quite a bit if that 40MW includes the cooling plant (which I think is atypical).
Panino Manino
Golden Member
"Game Cache" was ridiculous but easy to undertand marketing.
Now, "Rambo Cache"?
What "Rambo" is even supossed to mean?
So it was true that Raja left AMD, but AMD didn't left Raja...
(can't help but noticed Intel, like AMD, using italian inspired codenames)
What does this mean for the market, really?
Can Intel achieve some form of "leadership"? Nvidia have any reason to "fear"?
Now, "Rambo Cache"?
What "Rambo" is even supossed to mean?
So it was true that Raja left AMD, but AMD didn't left Raja...
(can't help but noticed Intel, like AMD, using italian inspired codenames)
What does this mean for the market, really?
Can Intel achieve some form of "leadership"? Nvidia have any reason to "fear"?
RetroZombie
Senior member
At least it’s not Rambus.
Watching the Intel presentation seams similar to some get smart episode:
Kaos agent: You will die now Smart, anything to say.
Maxwell: In 2022 Intel will be 50 times faster, would you believe it? 50 times faster.
Kaos agent: I find that pretty hard to believe.
Maxwell: What about 3 times in 2021.
Kaos agent: I don’t think so.
Maxwell: How about Intel 10nm cpus get downclocked to 4Ghz in 2020.
Kaos agent: Don’t make yourself ridicule Mr. Smart.
Anyway the 1000 EUs limit is it for single chip or group of chips?
If it’s for the group, from the picture it’s 154 for each chip, totaling 924 eus, if it’s for each chip than that’s near 6000 eus for the group which is impressive.
Watching the Intel presentation seams similar to some get smart episode:
Kaos agent: You will die now Smart, anything to say.
Maxwell: In 2022 Intel will be 50 times faster, would you believe it? 50 times faster.
Kaos agent: I find that pretty hard to believe.
Maxwell: What about 3 times in 2021.
Kaos agent: I don’t think so.
Maxwell: How about Intel 10nm cpus get downclocked to 4Ghz in 2020.
Kaos agent: Don’t make yourself ridicule Mr. Smart.
Anyway the 1000 EUs limit is it for single chip or group of chips?
If it’s for the group, from the picture it’s 154 for each chip, totaling 924 eus, if it’s for each chip than that’s near 6000 eus for the group which is impressive.
It's like a several hundred million dollar contract, so I don't know about that.
Because neither of us could possibly find out what is really going to happen, I will just say that we should agree to disagree, however lame that sounds =D
IntelUser2000
Elite Member
I think you misread. It's still much more efficient, its just trying to deliver 10x more performance, so it has to use more power, since you aren't going to see 10x gains in efficiency(that'll take 10-15 years, not 2).
2400 nodes with each node having 6x Ponte Vecchio GPU compute. Ponte Vecchio seems to be two boards with each board having 8 GPU dies.
1500W refers to 16 GPU dies plus the interconnect, plus the I/O, and plus the HBM memory. At best a single "whole" GPU section can't use more than 100W, while delivering 5TFlop compute. At 2000W, each GPU section can use no more than 125W.
When compute moves to MCM packaging with many chips on package, then we'll see TDP go up. HPC guys are expecting 1KW accelerators. Looks like they'll see it sooner than later.
Yea, $500 million.
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What does the size of contract have to do with profitability?
The contract is juicy enough to make it unrealistic they would be losing money on Aurora. There is some amount of PRness to it, but losing money no.
Ok, confused here. Why does losing imply great loss? As far as I'm concerned, anything less than break-even is a loss.
You can be less than break-even like Amazon was for a lot of the company's history without it really being a loss. There's some realization that it takes a certain investment of time and capital to generate a profit. If Intel comes out just under break-even I'd consider it a pretty big win for them because their past track record has involved pouring loads of money on these kinds of new ventures without them ever panning out.
If they're limiting themselves to a particular niche or smaller part of the market I think they have the opportunity to exceed. In the past they acted as if they needed to be as prominent or dominant in the new market segments as they were with desktop/server x86 and it led to a lot of products that weren't focused enough to really succeed in any specific area where Intel could gain a foothold.
ThatBuzzkiller
Golden Member
I'm not sure if it has been brought up recently here in this thread but Intel has unveiled their new oneAPI compute stack. The APIs offered include SYCL and DPC++ which are extensions to SYCL but as of writing this post their SYCL implementation is not listed as conformant by Khronos ...
So that officially makes it 3 competing compute API standards! We now have the following:
AMD: HIP kernel language -> hcc (Heterogeneous Compute Compiler) -> GCN ISA
Intel: DPC++ kernel language -> DPC++ Compiler -> SPIR-V binaries
Lastly but not least ...
Nvidia: CUDA kernel language -> nvcc (Nvidia CUDA Compiler) -> PTX ISA
It seems as if though Intel is attempting to ride off on the success of CUDA as well and just like AMD they are providing a source-to-source conversion tool to migrate from CUDA. SYCL alone is going to be a futile attempt in gaining traction so it appears that DPC++ is the only practical way to go about supporting Intel hardware ...
Unfortunately, their default compilation model is online compilation rather than offline compilation and using SPIR-V kernels as an intermediate representation (PTX is at least specific to a vendor) only exasperates this overhead. At least it's single source and there's extensions to target common CUDA kernels with a compatibility tool but I still don't see a way to write custom kernels with custom assembly ...
So that officially makes it 3 competing compute API standards! We now have the following:
AMD: HIP kernel language -> hcc (Heterogeneous Compute Compiler) -> GCN ISA
Intel: DPC++ kernel language -> DPC++ Compiler -> SPIR-V binaries
Lastly but not least ...
Nvidia: CUDA kernel language -> nvcc (Nvidia CUDA Compiler) -> PTX ISA
It seems as if though Intel is attempting to ride off on the success of CUDA as well and just like AMD they are providing a source-to-source conversion tool to migrate from CUDA. SYCL alone is going to be a futile attempt in gaining traction so it appears that DPC++ is the only practical way to go about supporting Intel hardware ...
Unfortunately, their default compilation model is online compilation rather than offline compilation and using SPIR-V kernels as an intermediate representation (PTX is at least specific to a vendor) only exasperates this overhead. At least it's single source and there's extensions to target common CUDA kernels with a compatibility tool but I still don't see a way to write custom kernels with custom assembly ...
Don't they have a contract to build this supercomputer in 2021? What happens if they don't deliver in time?
DrMrLordX
Lifer
Intel 740 on 10nm or 7nm? Only time will tell!
IronWing
No Lifer
Ya know, I started reading that thinking, "Intel's naming conventions have gotten so Byzantine it's hard to tell WTH is going on anymore, but this reads like a late 90s press release with Intel rehashing the Pentium name on low end chips" but then AGP came up and I was I knew I was had. 😛
Not that it would have been very successful anyway, but little over a year later the first GeForce came out. =D
Atari2600
Golden Member
I do have a serious point to this - Intel can roll out as many talking heads as they like all promising the world "game-changing" performance...
But till they deliver a product that can actually put frames on screens quick enough (without additional "interesting" artifacts) - I'll assume they are full of crap.
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