Intel Developer Forum 2014

[witeken]

I don't buy that 1.9 billion number -- looks like a typo.

Definitely possibluh, but I bet it is the layout transistor count. Such a big typo can't pass QA, right?

 

[Khato]

I don't buy that 1.9 billion number -- looks like a typo.

Considering that the Core M materials from last Friday stated 1.3 billion that'd be a bit of a typo - 3 and 9 aren't exactly close to one another. As well, that's roughly the translation I'd expect going from either schematic or layout to the number of 'individual' FinFETs on die. (Recall that an individual schematic transistor may well use multiple fins depending upon the necessary drive current.)

 

[Idontcare]

Considering that the Core M materials from last Friday stated 1.3 billion that'd be a bit of a typo - 3 and 9 aren't exactly close to one another. As well, that's roughly the translation I'd expect going from either schematic or layout to the number of 'individual' FinFETs on die. (Recall that an individual schematic transistor may well use multiple fins depending upon the necessary drive current.)

My thoughts exactly.

 

[Ajay]

Has anyone seen info on BW desktop CPUs (LGA, K series?). Is IDF kind of borked because of the upcoming F stepping Broadwells? I thought they might hold back on SKL, especially after seeing it's an 2015H2 part - but what's up with the apparent 'Zero' info on desktop BW?

 

[jpiniero]

Has anyone seen info on BW desktop CPUs (LGA, K series?). Is IDF kind of borked because of the upcoming F stepping Broadwells? I thought they might hold back on SKL, especially after seeing it's an 2015H2 part - but what's up with the apparent 'Zero' info on desktop BW?

Broadwell-K got delayed well into the second quarter. The time difference between Broadwell-K and the locked desktop Skylake quads may not be much. If they do a Skylake-K, it won't be until 2016.

 

[Arachnotronic]

Broadwell-K got delayed well into the second quarter. The time difference between Broadwell-K and the locked desktop Skylake quads may not be much. If they do a Skylake-K, it won't be until 2016.

I don't see a point in SKL-K...the Enthusiast platform will now be doing 6 cores bare minimum, which means that the value proposition of the K series just plummeted, IMO.

If I were upgrading from a SNB/IVB, I would go with an X99 board and a 5820 over a Z97 and a 4970K.

 

[Arachnotronic]

Considering that the Core M materials from last Friday stated 1.3 billion that'd be a bit of a typo - 3 and 9 aren't exactly close to one another. As well, that's roughly the translation I'd expect going from either schematic or layout to the number of 'individual' FinFETs on die. (Recall that an individual schematic transistor may well use multiple fins depending upon the necessary drive current.)

Maybe, but look at the differences between schematic and layout for, say, Haswell GT2 (per Anand):

The two numbers for the most common Haswell configuration, Haswell GT2 4C, are 1.4 billion schematic transistors and 1.6 billion layout transistors.

http://www.anandtech.com/show/7003/the-haswell-review-intel-core-i74770k-i54560k-tested/5

The difference here is 200 million transistors, but if 1.9 billion is not a typo, then the difference is a whopping 600 million.

Interesting if true. Not sure why Intel doesn't more readily advertise the layout number since it makes them look better.

 

[erunion]

I don't see a point in SKL-K...the Enthusiast platform will now be doing 6 cores bare minimum, which means that the value proposition of the K series just plummeted, IMO.

If I were upgrading from a SNB/IVB, I would go with an X99 board and a 5820 over a Z97 and a 4970K.

I disagree about value. The Devils Canyons are a great value, definitely up there with the 2500k.
Clock speed and single core performance is still key for gaming, so more cores in the E platform doesn't necessarily make it superior.

Haswell-E hasn't persuaded me to upgrade from my 2500k, I'm thinking my next rig will be a mainstream Skylake i7.

 

[Abwx]

Not sure why Intel doesn't more readily advertise the layout number since it makes them look better.

That s the contrary, more layout transistors means lacks in some caracteristics of the transistors, generaly in transconductance, that is the conduction slope of the transistor in function of the command voltage, as well as in Rdson wich is the minimal device resistance to conduction (resistance is the reciprocal of conductance), this could be solved by parrallelling two or more devices.

 

[Arachnotronic]

I disagree about value. The Devils Canyons are a great value, definitely up there with the 2500k.
Clock speed and single core performance is still key for gaming, so more cores in the E platform doesn't necessarily make it superior.

Haswell-E hasn't persuaded me to upgrade from my 2500k, I'm thinking my next rig will be a mainstream Skylake i7.

Interesting. Yeah, I can't really imagine a 2500K being inadequate for any gaming, esp. if overclocked.

 

[Khato]

http://www.anandtech.com/show/7003/the-haswell-review-intel-core-i74770k-i54560k-tested/5

The difference here is 200 million transistors, but if 1.9 billion is not a typo, then the difference is a whopping 600 million.

Interesting if true. Not sure why Intel doesn't more readily advertise the layout number since it makes them look better.

You can also find the same going back to Sandy Bridge numbers - http://www.anandtech.com/show/4818/counting-transistors-why-116b-and-995m-are-both-correct

Regardless, with FinFET there's the possibility for three numbers, all of which are technically the number of 'transistors' on die - schematic, layout, and number of individual fins. As evidenced by the above explanation for Sandy Bridge differences in schematic versus layout, there are many cases where routing optimizations result in a single schematic transistor gets split up into multiple layout transistors. Note that such doesn't necessarily have anything to do with drive strength given that with planar a single transistor could simply be made wider in order to meet that requirement. That's not the case with FinFETs however, as a single 'layout transistor' might actually consist of multiple fins... it's analogous to transistor width in a planar technology and hence it's kinda silly to be using number of fins as transistor count, but I could see it being done in this era of process technology density PR.

That s the contrary, more layout transistors means lacks in some caracteristics of the transistors, generaly in transconductance, that is the conduction slope of the transistor in function of the command voltage, as well as in Rdson wich is the minimal device resistance to conduction (resistance is the reciprocal of conductance), this could be solved by parrallelling two or more devices.

I'm reminded of people I work with that also like to repeat technical terms associated with the topic being discussed in order to sound like they understand what's going on. Of course in a conference room it's far easier to tell for sure, so instead I'll assume that the above is simply not being conveyed as intended and interpret it in the one way that makes sense.

When dealing with FinFETs, yes, each individual fin has a fixed trans-conductance which cannot be altered. If a single fin isn't adequate to meet timing then the layout has to use two fins for a single transistor. These cases are still typically considered to be a single 'layout' transistor since they are at the fin pitch distance and share the same gate/source/drain contacts - it's just analogous to using a planar transistor larger than the minimum width. After all, as explained above, the delta between schematic and layout transistor counts didn't really change for Intel between a planar and FinFET process and hence it's rather clear that the layout number being larger has nothing to do with drive current. No, it's purely a matter of other layout routing considerations (and/or resulting interconnect parasitic parameters) making it better to use multiple transistors in separate locations than a 'single' large one.

 

[witeken]

So wrapping up IDF, Intel showed a lot of interesting things that will launch in the near future, and although we didn't get to see a 10nm wafer, we did get to hear a lot of nice words about Skylake and its cable-less platform.

 

[Ajay]

Thanks witeken for keeping us up to date on the presentations :thumbsup:

 

[witeken]

Thanks witeken for keeping us up to date on the presentations :thumbsup:

It's been a great week for people who like technology ^_^.

 

[Abwx]

I'm reminded of people I work with that also like to repeat technical terms associated with the topic being discussed in order to sound like they understand what's going on. Of course in a conference room it's far easier to tell for sure, so instead I'll assume that the above is simply not being conveyed as intended and interpret it in the one way that makes sense.

You know that i m not talking randomly but still express some doubts, should i added that transconductance is called so because its the output/input caracteristic of a devices whose input command is expressed in volts while its corresponding output response is expressed as a current and that the resulting ratio Iout/Vin will thus be expressed as the reciprocal of the resistance, that is the conductance..??.

When dealing with FinFETs, yes, each individual fin has a fixed trans-conductance which cannot be altered. If a single fin isn't adequate to meet timing then the layout has to use two fins for a single transistor. These cases are still typically considered to be a single 'layout' transistor since they are at the fin pitch distance and share the same gate/source/drain contacts - it's just analogous to using a planar transistor larger than the minimum width. After all, as explained above, the delta between schematic and layout transistor counts didn't really change for Intel between a planar and FinFET process and hence it's rather clear that the layout number being larger has nothing to do with drive current. No, it's purely a matter of other layout routing considerations (and/or resulting interconnect parasitic parameters) making it better to use multiple transistors in separate locations than a 'single' large one.

If it has nothing to do with drive current then why the need to increase this caracteristic..?.

By parrallelling two device you increase the input capacitance wich will increase the losses so there s no reasons to increase the transistors count for such usages as its counter productive in matter of efficency unless you dont have the choice because otherwise (read low transconductance) your rising and falling hedges slopes will not be vertical enough hence increasing the crossconduction wich is even more dreadfull than input capacitance in respect of losses.

For the uninformed crossconduction occur when the two symmetrical devices are switching, one has not completely ended to conduct that the other one has already started conduction, during this short instant the devices are virtualy a short between the two power rails and the current is limited only by said devices intrinsical resistance, the higher the frequency the higher the crossconduction.

 

[Khato]

If it has nothing to do with drive current then why the need to increase this caracteristic..?.

By parrallelling two device you increase the input capacitance wich will increase the losses so there s no reasons to increase the transistors count for such usages as its counter productive in matter of efficency unless you dont have the choice because otherwise (read low transconductance) your rising and falling hedges slopes will not be vertical enough hence increasing the crossconduction wich is even more dreadfull than input capacitance in respect of losses.

For the uninformed crossconduction occur when the two symmetrical devices are switching, one has not completely ended to conduct that the other one has already started conduction, during this short instant the devices are virtualy a short between the two power rails and the current is limited only by said devices intrinsical resistance, the higher the frequency the higher the crossconduction.

The above simply shows that you haven't ever actually designed a complex CMOS circuit, or taken a course that discusses such. (Note that I'm referencing what I learned in such a graduate level course that touched on the subject since luckily I was spared getting into the structural design side of things.) Oh, and I really do like how now you're rambling about why it's a bad thing to parallel two devices when before you were saying that doing such was the reason for layout transistor count being higher than schematic:

That s the contrary, more layout transistors means lacks in some caracteristics of the transistors, generaly in transconductance, that is the conduction slope of the transistor in function of the command voltage, as well as in Rdson wich is the minimal device resistance to conduction (resistance is the reciprocal of conductance), this could be solved by parrallelling two or more devices.

Anyway, for the purposes here let's keep the discussion to planar devices. As per my earlier link, we already know that there was a marked difference between the number of schematic and layout devices. Now, as you've not so eloquently stated, when designing a circuit it's not a good idea to tie the output of two separate transistors together. And in a planar process there's no reason to do such given that you can increase the drive current of a transistor as much as you want by increasing its width. So what reason is there for there to be more layout transistors than there are schematic? Why don't you actually answer that? It should be easy considering that I already provided the answer...

(For everyone else, it's the fact that instead of using one transistor of 2x width it'll frequently make more sense to have 2 transistors of x width when the path in a circuit branches. Which is to say in schematic transistor m drives transistor n which in turn drives both o and p. If, in layout, o and p are quite a bit further away it's far more effective to have transistor m drive 2 smaller transistors in lieu of n which can be placed to keep the paths to both o and p shorter than if using a single transistor. Oh, and note that while I'm saying transistor here it's typically actual logic gates, or buffers, so on so such - it's all a delicate balancing act.)

 

[Abwx]

The above simply shows that you haven't ever actually designed a complex CMOS circuit, or taken a course that discusses such. (Note that I'm referencing what I learned in such a graduate level course that touched on the subject since luckily I was spared getting into the structural design side of things.) Oh, and I really do like how now you're rambling about why it's a bad thing to parallel two devices when before you were saying that doing such was the reason for layout transistor count being higher than schematic:

Seems to me that it s rather you that do not understand what i m talking about as there is no contradiction in my sayings, of course that parralleling transistors will increase the transistors layout count but not the electrical schematic transistor count functionalities wise.

Such practices, and i insist on it, are prove that a single transistor has not the desired caracteristic at a given location, hence multiplication of the devices wich is counterproductive in matter of dynamic power comsumption but can be a necessary compromise, you were very inspired to point that you were spared the structural side of things because the most basic insight is that in a CPU you dont have access to a wide range of devices caracteristics wise like you could do in a discrete design by using cmos with vastly different caracteristics in function of the purpose, hence those tricks that would be unthinkable in other areas unless also being limited by the components caracteristics.

Now, as you've not so eloquently stated, when designing a circuit it's not a good idea to tie the output of two separate transistors together.

If you had read what i wrote you would had noticed that i was saying tying two transistors inputs, that is two gates, this increase the input capacitance of the resulting device and increase the current demand sucked from the driving device, dont know if your mistake was intentional or not, though...

And in a planar process there's no reason to do such given that you can increase the drive current of a transistor as much as you want by increasing its width.
So what reason is there for there to be more layout transistors than there are schematic? Why don't you actually answer that? It should be easy considering that I already provided the answer...

You ll mod the sub threshold slope as well as the threshold voltage in the process as well as increasing the parasistic capacitances, that s not that simple as you sems to believe it, it can be done on a few instances but not for millions devices, modding your transistor will require modding the transistors that drive it and so on....

(For everyone else, it's the fact that instead of using one transistor of 2x width it'll frequently make more sense to have 2 transistors of x width when the path in a circuit branches. Which is to say in schematic transistor m drives transistor n which in turn drives both o and p. If, in layout, o and p are quite a bit further away it's far more effective to have transistor m drive 2 smaller transistors in lieu of n which can be placed to keep the paths to both o and p shorter than if using a single transistor. Oh, and note that while I'm saying transistor here it's typically actual logic gates, or buffers, so on so such - it's all a delicate balancing act.)

The less the transistors at equal electric schematic the better, all the rest are compromises where there is no gain , only less losses as i explained above, the balancing you re talking about is the point at wich the compromise is done, your exemple of transistors being "quite a bit further away" doesnt stand, dont forget that two transistors wont have the same caracteristics so it s no good to command two circuit with two transistors who are parraleled only at the gate level, it s better to use the same command signal than to create two signals that would be very slightly out of phase, same as modding transistors that require modding the previous one, that s not that simple otherwise the CPUs would work at 10Ghz.

 

[evangel76]

Core M is 1.3 Bi transistors.

Francois

 

[Khato]

Seems to me that it s rather you that do not understand what i m talking about as there is no contradiction in my sayings, of course that parralleling transistors will increase the transistors layout count but not the electrical schematic transistor count functionalities wise.

Such practices, and i insist on it, are prove that a single transistor has not the desired caracteristic at a given location, hence multiplication of the devices wich is counterproductive in matter of dynamic power comsumption but can be a necessary compromise, you were very inspired to point that you were spared the structural side of things because the most basic insight is that in a CPU you dont have access to a wide range of devices caracteristics wise like you could do in a discrete design by using cmos with vastly different caracteristics in function of the purpose, hence those tricks that would be unthinkable in other areas unless also being limited by the components caracteristics.

If you had read what i wrote you would had noticed that i was saying tying two transistors inputs, that is two gates, this increase the input capacitance of the resulting device and increase the current demand sucked from the driving device, dont know if your mistake was intentional or not, though...

Fair enough - that's what I get for attempting to interpret what you were saying as a response to my quote rather than a related tangent. I didn't recognize it immediately as I've never heard anyone call it cross-conduction before rather than the short circuit that it is. (And yeah, not even going to bother responding to the remainder as I believe I've explained the concepts adequately already.)

 

[Idontcare]

Core M is 1.3 Bi transistors.

Francois

Hi Francois, thanks for the confirmation.

To sate the curiosity of the forum, what is the fin count?

 

[witeken]

Hi Francois, thanks for the confirmation.

To sate the curiosity of the forum, what is the fin count?

He probably won't disclose undisclosed information.

 

[TuxDave]

Wow, this schematic vs layout vs fin count is intense. Fin count is no different from layout count at the end of the day. However the amount that fin/layout count differs from schematic count is higher on a finfet process (assuming iso-performance). Planar transistor can vary its width without counting as a new layout transistor up to a certain point. Finfets, without being able to vary the height of a fin, you can only add more fins.

The less the transistors at equal electric schematic the better, all the rest are compromises where there is no gain

Not really. For iso-schematic transistors, when you start scaling to larger drive strengths you can achieve better density, power and performance by "legging/splitting/parallelizing/whatever" the transistors instead of making a single gigantic* transistors.

* I chuckled to myself how I can see things in the um scale as "gigantic"

 

[Khato]

* I chuckled to myself how I can see things in the um scale as "gigantic"

Thanks for sharing that as it caused me to do the same

 

[witeken]

Mark Bohr 14nm presentation webcast

 

[mikk]

Is there also a webcast from the Broadwell or Gen8 presentation?