Discussion Intel current and future Lakes & Rapids thread

[uzzi38]

Do we have any real reputable source that leaked the +15% IPC uplift figure for Redwood Cove?

No and it doesn't have anything like that.

 

[uzzi38]

ES2 should be out by now, using RPL development cycle as a guide line. Looks like ES-2 should start being sent out ~8 months before launch. ES-1s on the other hand should have been sent out a year before launch, so ye only like 3-5 months ago I'm guessing is when ES-1 samples were sent out.
RPL was stated to have a timeline of 6 months shorter than Alder Lake, since RPL is more of a refresh, but I'm guessing most of the time saving procedures came during the design phase since rather than stuff like validation.
We know MTL powered on in end of april 2022, and power on to launch is ~15 months gap. If this held true, MTL should be launching in July, or slightly more than half way into 2023. However that is pretty doubtful to happen, so I'm assuming there were a bunch of issues during the power on phase, which is why ES-1 samples only started coming out some what recently like ~3 months ago, since if they were on track they should be releasing July of 2022 rather than 2 months later in ~November of last year.

ES1 being available to OEMs is MUCH more recent than you think.

That's the last I'm going to say on this topic for a while now.

 

[IntelUser2000]

It's much tougher to hide the actual volume in desktop versus mobile.

Lots of speculations.

Desktops need 8+16 to be not a sidegrade in all scenarios and not be lower in single thread either. 8+16 with little bit of less clocks equals the last generation. What is the point? Then what does 6+16 do? There's no point of 6+16 Meteorlake-S in any K lineup.

It's better to wait for Arrowlake because it also helps them advance IDM 2.0 objectives rather than sticking with what's the last gen.

Ideally Meteorlake should have been mid this year at the latest but at least for desktops that ain't happening, so why stick to that? I don't get people. Arrowlake is much, much better, and it allows Arrowlake to come earlier/not be impacted by Meteorlake-S delay.

I'm sick of the "I want it, and I WANT IT NOW!!" crowd. Do you like throwing money away every year or something?

 

[Hulk]

I'm sick of the "I want it, and I WANT IT NOW!!" crowd. Do you like throwing money away every year or something?

When I was younger I was of the mindset that I'm not upgrading until absolutely necessary. As I've gotten older I'm less inclined to wait on things that I want, within reason. Computers are a work tool and a hobby for me at this point in my life and as such I'm more willing to indulge myself now and then.

Do we have any real reputable source that leaked the +15% IPC uplift figure for Redwood Cove?

No.

Intel's Arrow Lake Architecture to Have Major IPC Gains Over Alder Lake

It's not coming out until 2024, fingers crossed, but Arrow Lake will be the true successor to Raptor Lake with major gains in both IPC and efficiency.

www.extremetech.com

 

[Glo.]

https://twitter.com/x/status/1630607292126330882

MTL-P ES1 all core P core turbo - 3.6 GHz.

 

[Dayman1225]

https://twitter.com/x/status/1630607292126330882

MTL-P ES1 all core P core turbo - 3.6 GHz.

1T supposedly 4ghz

https://twitter.com/x/status/1630609490369454080

 

[Hulk]

1T supposedly 4ghz

https://twitter.com/x/status/1630609490369454080

Now this rumor "feels" legit. Meteor Lake on Intel 4 ES1 at 3.6GHz MT, 4GHz ST. That would seem to corroborate why we won't be seeing this part on the desktop.

 

[mikk]

Now this rumor "feels" legit. Meteor Lake on Intel 4 ES1 at 3.6GHz MT, 4GHz ST. That would seem to corroborate why we won't be seeing this part on the desktop.

Isn't it a reasonable high clock speed considering it's ES1? There are usually big uplifts going from ES1 to ES2 and sometimes even from ES2 to QS. 12900K ES2 reached 4600 Mhz on 1C/2C, the final 12900K reached 5.1/5.2 Ghz, see here: https://www.igorslab.de/en/exclusive-data-to-intel-alder-lake-s-hot-fight-with-amd/

ES1 doesn't have to run on high clock speeds. 4 Ghz ES1 MTL is higher than Icelake-U i7-1065G7 retail assuming 4Ghz is accurate.

 

[Hulk]

Isn't it a reasonable high clock speed considering it's ES1? There are usually big uplifts going from ES1 to ES2 and sometimes even from ES2 to QS. 12900K ES2 reached 4600 Mhz on 1C/2C, the final 12900K reached 5.1/5.2 Ghz, see here: https://www.igorslab.de/en/exclusive-data-to-intel-alder-lake-s-hot-fight-with-amd/

ES1 doesn't have to run on high clock speeds. 4 Ghz ES1 MTL is higher than Icelake-U i7-1065G7 retail assuming 4Ghz is accurate.

I think we also have to take into account not only the predicted clock speed of the new part coming to market but the performance of the part it is supposed to succeed. For example, Alder Lake was the next gen after Rocket Lake, which was an admittedly low bar so 5.1 for retail Alder provided a good bump in both ST and MT performance over Rocket.

With the significant increase in both clocks and cache Raptor also provided a nice bump from Alder.

But, the super high clocks of Raptor provide a quite high bar for Meteor. Even if Meteor could hit 5GHz retail upon release it would only equal Raptor in performance. Yes, I know efficiency would be much better but that doesn't look good on the side of the box, "Just as fast and more efficient."

Meteor could have succeeded Alder Lake but not Raptor Lake. Raptor clocks are just too insanely high.

So now what do you do if you are Intel and are faced with two likely options?

1. Release Meteor Lake on the desktop knowing that performance will at best equal Raptor Lake.

2. Release Meteor Lake for mobile increasing mobile performance and efficiency and Release Raptor Refresh as the other part of 15th Gen. Intel. Raptor Refresh will obviously be a higher performing part than Raptor (current).

The benefit of option two other than continuing to increase performance for both mobile and desktop is that this gives Intel time to refine the Intel 4 process so clocks are where they need them to be for Arrow Lake.

 

[mikk]

Intel struggled a lot on initial 10nm node and the first 14nm Broadwell-U, they barely could hit 4 Ghz on a final retail chip. Pretty sure TGL-U didn't clock 4Ghz on ES1. 4 Ghz MTL mobile ES1 is quite good to me, clock speed is not the big problem if true. Even some Raptor desktop ES1 didn't. Raichu referred to MTL-P ES2. The ES1 clock speed from above is no disproof. Bullsh1t_Buster doesn't have ES2 clock speeds, only the target which he didn't specified. He is not as good as Raichu when it comes to Intel leaks. I think Bullshit_bust is not aware that ES1 and ES2 clock speed could heavily differ. Especially on a very new node and first chiplet. The learning curve can be bigger.

 

[scannall]

Intel struggled a lot on initial 10nm node and the first 14nm Broadwell-U, they barely could hit 4 Ghz on a final retail chip. Pretty sure TGL-U didn't clock 4Ghz on ES1. 4 Ghz MTL mobile ES1 is quite good to me, clock speed is not the big problem if true. Even some Raptor desktop ES1 didn't. Raichu referred to MTL-P ES2. The ES1 clock speed from above is no disproof. Bullsh1t_Buster doesn't have ES2 clock speeds, only the target which he didn't specified. He is not as good as Raichu when it comes to Intel leaks. I think Bullshit_bust is not aware that ES1 and ES2 clock speed could heavily differ. Especially on a very new node and first chiplet. The learning curve can be bigger.

Engineering samples are just to prove and validate the architecture. The speeds they run at are pretty meaningless when it comes to what will actually ship. The guessing game is fun and all, but solely for entertainment value. No serious discussion need apply.

 

[Hulk]

Intel struggled a lot on initial 10nm node and the first 14nm Broadwell-U, they barely could hit 4 Ghz on a final retail chip. Pretty sure TGL-U didn't clock 4Ghz on ES1. 4 Ghz MTL mobile ES1 is quite good to me, clock speed is not the big problem if true. Even some Raptor desktop ES1 didn't. Raichu referred to MTL-P ES2. The ES1 clock speed from above is no disproof. Bullsh1t_Buster doesn't have ES2 clock speeds, only the target which he didn't specified. He is not as good as Raichu when it comes to Intel leaks. I think Bullshit_bust is not aware that ES1 and ES2 clock speed could heavily differ. Especially on a very new node and first chiplet. The learning curve can be bigger.

Perhaps yields of functional parts is low.

 

[IntelUser2000]

I appreciate when sites like Anandtech doesn't post every rumors and leaks.

Engineering samples can be easily off by 20% in clocks. Iris Xe for example had performance way below Icelake's GPU, when the final version came out to be nearly 2x the performance.

Verdict: Much ado about nothing, just like lots of things are nowadays.

 

[Exist50]

Engineering samples are just to prove and validate the architecture. The speeds they run at are pretty meaningless when it comes to what will actually ship. The guessing game is fun and all, but solely for entertainment value. No serious discussion need apply.

Well, performance validation is absolutely a thing. Companies would definitely prefer early ES chips to run at full speed. But for an immature process and design, that's just not realistic.

I this both these rumors are reasonable. Peak clocks around 4GHz for ES1, and around 5GHz for ES2. QS will be the important one though. As well as what the overall binning looks like.

 

[mikk]

Engineering samples are just to prove and validate the architecture. The speeds they run at are pretty meaningless when it comes to what will actually ship. The guessing game is fun and all, but solely for entertainment value. No serious discussion need apply.

ES1 and even ES2 doesn't have to run on the shipping clock speed or limit, 4 Ghz is something early 10nm and 14nm couldn't do however. 4 Ghz for ES1 sounds promising therefore in this early stage of Intel 4.

 

[Hulk]

QS will be the important one though. As well as what the overall binning looks like.

What does "QS" stand for again?

Also we really have no idea what "Intel 4" means in terms of feature size. Intel 7 is based off of 10nm, which itself became a nebulous measurement many nodes ago. Intel 4 could really just be a minor improvement to Intel 7. Too bad we never get to know transistor density anymore because that would provide more information than these fictitious node names.

Intel actually increased Transfer Gate Pitch with Coffee Lake with 14++ to increase clocks (and leakage) at the expense of die area (density) and idle power (from Anandtech). See chart below.

My point is that Intel really only needs to tweak Intel 7 for slightly better density and efficiency (power) to call it Intel 4. None of this relates to actual numbers anymore. The only indication we have of how a process is really "working" is how many cores do they fit on it and what is the throughput of those cores. If they are squeezing more, higher IPC cores, or even the same number of higher IPC cores then density is increasing. Intel used to love touting those numbers or at least density increases. Not so much now with TMSC around.

So playing by the new rules, Intel could have called 14+++ Intel 12 or something like that, and then 14+++++ Intel 10, etc... This tend hide process delays. They kind of did that with Intel 7, still really 10nm but deemed to be "Intel 7." The bottom line is getting rid of the + system is a good marketing idea as Intel 7, Intel 4, Intel 20A, Intel 18A, are just representations of density/iso frequency decreasing. The probably should have created finer graduations, Intel 7, Intel 6, Intel 5, like TMSC does to create the impression that they are really cranking along with these process shrinks!

Instead we consider the last process at 14nm the "true" 14nm. Same with 10nm except now that will be Intel 7. So we really have Tiger Lake ending 10nm and RPL R closing the door on Intel 7. So it doesn't "feel" like 10nm+++++++++++++++++.

Minimum Feature Size	Based on measurements of the die, out of the 26mm2 increase from Kaby Lake 4 core, 91.5% is for CPU area, and the rest likely accounting for the change in gate pitch across the whole processor.
	22nm	14/14+	14++
Transistor Fin Pitch	60​	42​	42​
Transistor Gate Pitch	90​	70​	84​
Interconnect Pitch	80​	52​	52​
Transistor Fin Height	34​	42​	42​

 

[Kocicak]

What does "QS" stand for again?

Qualification sample

 

[Glo.]

Semi off-topic.

https://twitter.com/x/status/1630926045019766786

Remember what I have written previously about Windows 12, AI in operating system, and what role will it play in it, and why big APUs/SOC will become mainstream, and why Intel is the main driver here?

 

[Tigerick]

Semi off-topic.

https://twitter.com/x/status/1630926045019766786

Remember what I have written previously about Windows 12, AI in operating system, and what role will it play in it, and why big APUs/SOC will become mainstream, and why Intel is the main driver here?

The article also mentioned about AMD's involvement. In fact, AMD will ship Phoenix based notebooks next month. As for Intel's MTL, it seems Intel will only ship it early next year based on progress so far

 

[Dayman1225]

https://twitter.com/x/status/1630957551784439810

raichu appears to have posted for clocks at a given voltage for redwood cove (MTL Pcore).

 

[Dayman1225]

edit

 

[Hulk]

What are the differences between QS, ES1, and ES2? Both in form and purpose?

 

[DrMrLordX]

What are the differences between QS, ES1, and ES2? Both in form and purpose?

Engineering samples tend to have bugs, and may feature lower clocks or weaker v/f curves than final product. QS needs to be as close to a retail sample as possible to give OEMs/major customers time and opportunity to figure out how to best use the provided hardware (spec cooling, power, etc.)

 

[Kocicak]

What are the differences between QS, ES1, and ES2? Both in form and purpose?

A Sampling of Sample Processors | The CPU Shack Museum

According to this article, several samples are made:

• mechanical
• thermal - contain heater instead of chip
• ES1 - contain silicone, slow and buggy
• ES2 - contain silicone, almost final clocks and a lot less buggy
• QS - final silicone, send out to partners or reviews.

 

[Exist50]

https://twitter.com/x/status/1630957551784439810

raichu appears to have posted for clocks at a given voltage for redwood cove (MTL Pcore).

Raichu delivering the goods. Notably, this is PDK0.8 (i.e. not final), and the voltage only goes up to 1.1V, which is pretty low. Assuming this represents ES2 silicon, I think final clock speeds in the mid-5GHz range for mobile chips are very reasonable.

That said, the VF curve is a bit weird. There's a spike for that last 0.02V, when you'd expect the opposite.