Discussion Intel current and future Lakes & Rapids thread

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Exist50

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raichu appears to have posted for clocks at a given voltage for redwood cove (MTL Pcore).
Raichu delivering the goods. Notably, this is PDK0.8 (i.e. not final), and the voltage only goes up to 1.1V, which is pretty low. Assuming this represents ES2 silicon, I think final clock speeds in the mid-5GHz range for mobile chips are very reasonable.

That said, the VF curve is a bit weird. There's a spike for that last 0.02V, when you'd expect the opposite.
 
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deasd

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Round 1. FIGHT!




No profanity in tech.
This include profanity from a twitter post you referenced.


esquared
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Geddagod

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He said that about the 1% IPC gain from RWC, not about the V/F curve.redacted is trying waaaay to hard, and this is a bit of a tangent, but I swear tech twitter just loves to mis quote or quote people out of context...





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esquared
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Exist50

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I think 1% IPC gain would be a perfectly reasonable prediction for RWC. Extremely underwhelming, of course, but I think Raichu's right on the money here.






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esquared
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Exist50

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View attachment 77426
Just something interesting
And thus the problem with RWC. Extrapolated out, their peak frequencies would be roughly equal, which is bad enough by itself without IPC gains. But even that assumes Intel 4 can hit similar peak voltages as Intel 7, which is unlikely. At a more realistic limit in the 1.2-1.3V range, you're squarely in the mid-5GHz territory I'm expecting us to see in shipping products.
 

AMDK11

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These rumors look weird. On the one hand, according to rumors, the 14th gen RaptorLake is to be refreshed, which Intel does not mention and suggests that the 14th gen is Meteorlake.

According to rumors, RedwoodCove is almost 0% progress in IPC, while the chief engineer of Cove claims that after RaptorLake we will see bigger jumps than before.

Personally, I'll wait for official info.
 
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Geddagod

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These rumors look weird. On the one hand, according to rumors, the 14th gen RaptorLake is to be refreshed, which Intel does not mention and suggests that the 14th gen is Meteorlake.
I mean 14th gen is still likely MTL, since rumors only say RPL-R for desktop not mobile.
According to rumors, RedwoodCove is almost 0% progress in IPC, while the chief engineer of Cove claims that after RaptorLake we will see bigger jumps than before
Oh ye I remember that interview. He said after Raptor Lake and Meteor Lake that there will be bigger and bigger jumps. Even that kinda subtly hints RPL and MTL weren't going to be as big jumps in IPC than perhaps we thought earlier.
Personally, I'll wait for official info.
Speculation is fun though ; )

Also I forgot to add, if anyone knows a source for Zen 4 V/F curve? I used skatterbench for the 13900k (RPC) but couldn't find one for Zen 4. There was a curve that started from like 4 GHz or something, but I also didn't want to add that because of the lack of data points and since there was like no data for the lower end of the V/F curve.
 

IntelUser2000

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Also we really have no idea what "Intel 4" means in terms of feature size. Intel 7 is based off of 10nm, which itself became a nebulous measurement many nodes ago. Intel 4 could really just be a minor improvement to Intel 7. Too bad we never get to know transistor density anymore because that would provide more information than these fictitious node names.

Hulk, you are mistaken here. They fully detailed the Intel 4 process at IEDM. You must have missed it. It's a full node jump, in terms of performance equal to going from 14nm to 10nm. We're losing on the traditional density gains, but still significant.

Here's one article: https://fuse.wikichip.org/news/6720/a-look-at-intel-4-process-technology/

Meteorlake shows the shrink is between 30-40%. Since Meteorlake does have core changes(however minute it may be), 40%(or 1.67x) density gain is what we're seeing now. That is a proper shrink.

They are saying 2x is possible but talking about things as depopulating the fins to do so. 2x might be possible if they forego the transistor performance improvements and focus on density.

Also, we know the Intel 3 is a much minor change. Thus the smaller number changes. The big one is 20A, hence the big name change again. There is logic here even though lot has been lost compared to a decade ago(not like Samsung calling 3 similar nodes way different names for example).

Another thing is shrinks offer capacitance reduction for power reduction for transistor. For example while the original 10nm wasn't faster, it still offered power reduction. + like the 14nm and 10nm variants can't do that(at least in a major way). Sure the transistor is higher performance, but the way to lower power without significant changes is by lowering the voltage, which is not something you can always do as modern CPUs are very close to the threshold where transistors operate.

Capacitance reduction on node changes offer the power reduction without needing to temper with voltages. Intel 4 does that. Intel 10SF, ESF, 7 does not.

Another way of thinking is +, SF, ESF, Intel 7 is like Raptor Cove. Slight changes. Intel 4 is like Sunny/Golden/Lion Cove. Big changes that encompass important parts of the core.
 
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Hulk

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Hulk, you are mistaken here. They fully detailed the Intel 4 process at IEDM. You must have missed it. It's a full node jump, in terms of performance equal to going from 14nm to 10nm. We're losing on the traditional density gains, but still significant.

Here's one article: https://fuse.wikichip.org/news/6720/a-look-at-intel-4-process-technology/

Meteorlake shows the shrink is between 30-40%. Since Meteorlake does have core changes(however minute it may be), 40%(or 1.67x) density gain is what we're seeing now. That is a proper shrink.

They are saying 2x is possible but talking about things as depopulating the fins to do so. 2x might be possible if they forego the transistor performance improvements and focus on density.

Also, we know the Intel 3 is a much minor change. Thus the smaller number changes. The big one is 20A, hence the big name change again. There is logic here even though lot has been lost compared to a decade ago(not like Samsung calling 3 similar nodes way different names for example).

Another thing is shrinks offer capacitance reduction for power reduction for transistor. For example while the original 10nm wasn't faster, it still offered power reduction. + like the 14nm and 10nm variants can't do that(at least in a major way). Sure the transistor is higher performance, but the way to lower power without significant changes is by lowering the voltage, which is not something you can always do as modern CPUs are very close to the threshold where transistors operate.

Capacitance reduction on node changes offer the power reduction without needing to temper with voltages. Intel 4 does that. Intel 10SF, ESF, 7 does not.

Another way of thinking is +, SF, ESF, Intel 7 is like Raptor Cove. Slight changes. Intel 4 is like Sunny/Golden/Lion Cove. Big changes that encompass important parts of the core.

Well while I'm on roll of being wrong I might as well really go for it.
Here's another one of those charts I've been developing for 30 years. I've put my predictions at the top in red font. Gonna regret this!
 

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IntelUser2000

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Well while I'm on roll of being wrong I might as well really go for it.
Here's another one of those charts I've been developing for 30 years. I've put my predictions at the top in red font. Gonna regret this!

That's pretty good overall.

I'm expecting 6-8% gains for the P cores in Meteorlake's Redwood Cove cores, and close to 30% for Lion Cove. The E core gains are likely going to be higher than the P core gains. Wouldn't be surprised at solid double digit gains on the Crestmont E cores for Meteorlake. Probably another 30% on top with Skymont cores for Arrowlake.

That'll result in P and E cores only having a 30% iso-clock/thread gap, versus 45-50% for today.
 
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coercitiv

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That chart doesn't look like speculation to me. Where are you getting that claim from?
It's the result of leakers being intentionally cryptical on Twitter, while also combining leaks with speculation in subsequent posts. Raichu answered he was speculating with respect to his low digit IPC increase for RWC, and others took it as speculation for the voltage curve. Even I don't know what to make of it, except for the fact nobody sane would SPECULATE with 0.02V increments, so I'm inclined to believe his v/f curve is a leak or extrapolation based on some leaked v/f points.
 

Exist50

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It's the result of leakers being intentionally cryptical on Twitter, while also combining leaks with speculation in subsequent posts. Raichu answered he was speculating with respect to his low digit IPC increase for RWC, and others took it as speculation for the voltage curve. Even I don't know what to make of it, except for the fact nobody sane would SPECULATE with 0.02V increments, so I'm inclined to believe his v/f curve is a leak or extrapolation based on some leaked v/f points.
I'm inclined to think the whole thing is legit. Where else would the reference to Intel's internal naming convention (Intel 4 -> p1276.3) come from?
 
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sasankgs

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Well while I'm on roll of being wrong I might as well really go for it.
Here's another one of those charts I've been developing for 30 years. I've put my predictions at the top in red font. Gonna regret this!
Why did you put "Intel 4" next to Arrow Lake ? Isn't it 20A or external node ?
 

Hulk

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Why did you put "Intel 4" next to Arrow Lake ? Isn't it 20A or external node ?

That was supposed to be red font as my prediction. I think Intel is going to "fall in love" with Intel 4 like they do with every process once they get it under their thumb and subsequently use it for Arrow Lake as well. They haven't used a process for one generation in ... well a really long time.
 

Glo.

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I'm inclined to think the whole thing is legit. Where else would the reference to Intel's internal naming convention (Intel 4 -> p1276.3) come from?
I think I believe Raichu on this topic more, for some reason ;).

Despite the fact ES1 is already in the wild.
 

DrMrLordX

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Go back read that thread again. Raichu said the IPC of RWC was his speculation. V/F curve was not his speculation. He said he got that info from an Intel dev board.

Then exactly what was it that bs buster complaining about? I know what I saw.
 

Geddagod

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That was supposed to be red font as my prediction. I think Intel is going to "fall in love" with Intel 4 like they do with every process once they get it under their thumb and subsequently use it for Arrow Lake as well. They haven't used a process for one generation in ... well a really long time.
I'm guessing it's going to be hard to add a bunch of architectural improvements, especially a traditional widening of the core, while using Intel 4 compared to Redwood Cove. One could argue Intel essentially did it with Intel 7 vs Intel 10nm ESF (GLC vs SNC) but it's also true that if you want to keep on expanding the core, additional die overhead keeps on increasing and performance benefits also lessen. Plus, I think GLC is kinda infamous for being kind of 'bloated', core-to-core (even if 8C vs 8C it's not as bad) compared to zen 4 or even zen 3, which uses a similar 7nm class node.
 

Glo.

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Then exactly what was it that bs buster complaining about? I know what I saw.
He used it, out of context, to simply tell everybody what he thinks about Raichu's credibility.

I do believe that BS Buster is correct on the topic ES1 being available. But I do not believe Raichu has made stuff up in the topic of voltage/frequency.