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Discussion Intel current and future Lakes & Rapids thread

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Mopetar said:
I don't really get what anyone is complaining or griping about. Previously AMD didn't even offer AVX-512 and just lost those benchmarks by default. Now they actually offer a competitive alternative.
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You're right that it's probably not worth the griping, but it's pretty annoying to have the forum filled with weeks or even months of insane hyperbole, only to pretend it never happened when the reality turns out to be much more mundane.

Really has nothing to do with the merits of the chips themselves, just metacommentary on the forum.
 
nicalandia said:
When Phoronix tested the Ryzen vs Rocket Lake and between Genoa and Ice Lake that was the case, but Sapphire Rapids was just recently released. So we just got this.
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And what's meaningfully changed? Seems to behave more or less like Sunny Cove did. Maybe with even less of a clock penalty, but that never really mattered in testing.
 
nicalandia said:
Do you have comprehension issues? For team working on AVX-512 Genoa is the clear winner
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I read and understand English very well since it's my native language. I can't believe you're going to force me to do it, but this is from a post you made over a week ago:

Performance is allover the place, but what surprises me is the AVX-512 Performance, AMD is beating them really bad.
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Link

That statement clearly implies that you believe Genoa's AVX-512 performance is better than Intel's, when it clearly isn't.

As @Exist50 (and Phoronix) explained, the reason why Genoa pulls ahead in many of these benchmarks has nothing to do with its AVX-512 performance, and everything to do with its superior core/thread count and memory bandwidth advantage over SPR.

SPR has a native AVX-512 implementation that is superior to Genoa's, which is why it's able to compete and even beat Genao in many benchmarks despite having significantly less cores/threads.

This is similar to Raptor Lake vs Zen 4 on desktop. Zen 4 has more cores/threads, but Raptor Lake has higher throughput and (unlike SPR) higher memory bandwidth which can nullify Zen 4's core advantage in heavy vectorized workloads.
 
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Carfax83 said:
That statement clearly implies that you believe Genao's AVX-512 performance is better than Intel's, when it clearly isn't.
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Well it is, didnt you see the benchmarks? In more cases thant not AMD is the clear winner. Hence the Geomean The Top Genoa SKU is beating the Top SPR-SP SKU.

AMD provides better AVX-512 Performance at a lower price point.
 
nicalandia said:
Well it is, didnt you see the benchmarks? In more cases thant not AMD is the clear winner. Hence the Geomean The Top Genoa SKU is beating the Top SPR-SP SKU.

AMD provides better AVX-512 Performance at a lower price point.
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You seem unable or unwilling to understand the difference between absolute performance and actual AVX512 performance. Genoa outperforms SPR in absolute performance due to having far more cores/threads, cache and memory bandwidth. SPR outperforms Genoa in actual AVX512 performance however, because it can issue 2x 512 bit instructions per cycle vs 1 512 bit instruction per cycle for Genoa.
 
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Carfax83 said:
You seem unable or unwilling to understand the difference between absolute performance and actual AVX512 performance. Genoa outperforms SPR in absolute performance due to having far more cores/threads, cache and memory bandwidth. SPR outperforms Genoa in actual AVX512 performance however, because it can issue 2x 512 bit instructions per cycle vs 1 512 bit instruction per cycle for Genoa.
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that's not even correct, Zen4 can do 2 x 512bit operations a cycle , but it can only do 1x 512bit FMA and it only has 1/2 the load store bandwidth. So it all depends on the exact instruction mix and register to memory ratio as to how much more performant per clock GC is then Zen 4.
 
itsmydamnation said:
that's not even correct, Zen4 can do 2 x 512bit operations a cycle , but it can only do 1x 512bit FMA and it only has 1/2 the load store bandwidth.
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Load/Store is a big factor in HPC code performance, which is why Intel doubles them every time they doubled the vector units(AVX, AVX2, AVX-512), same with FMA.

Besides, the argument is nothing more than a e-peen contest anyway. "My SIMD*** is bigger than yours!"

The reality is that it's complex especially due to the fact that Sapphire Rapids was seriously delayed. So the purchase decision is if you need that, which will likely be true if you are an HPC customer, and doubly true with HBM variant.
 
I think the best way to look at it is SPR is a specialist chip with plenty different highly throughput optimized accelerators (as far as CPUs go anyway), AVX-512 being just one of them.

The Zen core in Genoa is more along the line of traditional CPUs, while AVX-512 is supported the throughput it requires is not the focus at all. Instead it's rather well integrated within the existing restraints and plays along well enough with the rest of the chip.

So in AVX-512 theoretical peak performance per core and frequency I'd expect SPR to far much better than Genoa. It's for mixed workloads so typical for CPUs as well as the difference in amounts of cores and power efficiency that complicate the overall picture.
 
Peak performance per core in most of server/HPC application means nothing by itself. The most meaningful metrics for these cases are perf/W, perf/$, perf/socket. Yes, it is a interesting exercise. In practice, if it does not met the other metrics' targets, it is not useful.
 
Screenshot_2023-01-21-17-59-53-872_com.google.android.youtube.jpg

He just try to help Intel marketing people get the words out 🙄

Intel did say GNR was taped in Q2 last year, so now still in designing time, which should be ready for production in Q2 next year.

The slide did say MTL were having yield issues: Really meh, after so many years in 7nm process, they still cannot get past 6 big cores in MTL. So my question is how long Intel going to bring 44 p cores in Intel 3 to acceptable yields and ship it?

Come on Intel, I don't want to lose the bet, please ship GNR before end of 2025😛
 
Tigerick said:
The slide did say MTL were having yield issues: Really meh, after so many years in 7nm process, they still cannot get past 6 big cores in MTL. So my question is how long Intel going to bring 44 p cores in Intel 3 to acceptable yields and ship it?
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The same way they shipped Ice Lake-SP: set fire to a ton of wafers for very little product.

Come on Intel, I don't want to lose the bet, please ship GNR before end of 2025😛
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After their execution on both Ice Lake-SP and Sapphire Rapids, you shouldn't get your hopes up.
 
DrMrLordX said:
The same way they shipped Ice Lake-SP: set fire to a ton of wafers for very little product.



After their execution on both Ice Lake-SP and Sapphire Rapids, you shouldn't get your hopes up.
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speaking of fire.... The 13900k and 13900ks chips are on fire as well, temps and power usage both off the charts.

Should we call Intel a "fired up" company ?
 
DrMrLordX said:
After their execution on both Ice Lake-SP and Sapphire Rapids, you shouldn't get your hopes up.
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That's assuming they didn't learn anything from those experiences. I think they have a better chance now coz a woman (https://twitter.com/sandralrivera) is getting everyone to communicate with regular meetings. Lisa Su did the same for AMD and for the Cell CPU before that (even though she probably regrets making so many developers complain about that hard to program CPU).
 
Tarkin77 said:
probably from here

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He's up to his usual BS again. Not worth listening to.

That said, it should be obvious that Sierra Forest AP would have hundreds of cores. You can fit ~4 Atom cores in the space of a single big core. If GNR actually has 132/128 Redwood Cove cores, then that would translate to ~512 Crestmont. The only question is if Intel thinks it's worth cramming that many in a single socket.
Tigerick said:
The slide did say MTL were having yield issues: Really meh, after so many years in 7nm process, they still cannot get past 6 big cores in MTL.
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And yet it also claims they're not necessarily an Intel 4 problem, and GNR is on track. Been saying for ages now that MTL execution is a mess, and it sounds like that hasn't changed much. Will have to see how GNR goes, but 2024 is already disappointingly late for something as lackluster as RWC.
 
igor_kavinski said:
That's assuming they didn't learn anything from those experiences. I think they have a better chance now coz a woman (https://twitter.com/sandralrivera) is getting everyone to communicate with regular meetings. Lisa Su did the same for AMD and for the Cell CPU before that (even though she probably regrets making so many developers complain about that hard to program CPU).
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Why would Rivera have any direct impact on the silicon development? She leads the business group, not the engineering team. She could kneecap the engineering team by lack of funding, frequent spec changes, etc., but the absolute best case scenario would be simply giving the engineering team the time and resources they need to do their jobs.
 
Exist50 said:
Why would Rivera have any direct impact on the silicon development?
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According to an article posted around here, she was tasked by Gelsinger to oversee the whole thing when the delays started piling up.

Exist50 said:
but the absolute best case scenario would be simply giving the engineering team the time and resources they need to do their jobs.
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Assuming they work well together. I think Rivera's task is to ensure there is proper co-ordination within teams and between the different teams involved. Regular progress updates and making sure they are on track and solving the problems before they become too big to handle.
 
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