Discussion Intel current and future Lakes & Rapids thread

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jpiniero

Lifer
Oct 1, 2010
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Exist50 said:
Historically, those low end SKUs are basically "I need PCIe lanes for a file server" kind of offerings.
Click to expand...

That was more Xeon E. You can still buy those but who knows if Intel will refresh it with anything beyond Rocket Lake.

One chiplet Epyc probally makes more sense.
 
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Hitman928

Diamond Member
Apr 15, 2012
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nicalandia said:
Do any of you know what's going in here? Even with the OpenVIMO AMX boost(They are real, you can click on the link and see them) the 8490H is getting beat pretty soundly by two 9374F Genoa CPUs(64C total, so it's a 64C vs 60C)

View attachment 74420

AMD Genoa 2S 9374F vs 1P Intel Xeon SPR 8490H
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Their Epyc system spans the 64 cores over two CPUs, so the all core boost clocks should be much higher for the Epyc CPUs. Power consumption should be higher for the Epyc system as a result as well.
 
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Exist50

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Aug 18, 2016
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jpiniero said:
That was more Xeon E. You can still buy those but who knows if Intel will refresh it with anything beyond Rocket Lake.

One chiplet Epyc probally makes more sense.
Click to expand...
By "file server", I really meant a storage rack. Basically any use case where you just need the IO bandwidth, but the CPU is more or less irrelevant.
 
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nicalandia

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Jan 10, 2019
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Hitman928 said:
I don’t know enough about this software or how the accelerator works to really say. It does look strange though.
Click to expand...
That's the Only App in there that is taking advantage of Intel AMX Intructions... It's weird that 1P is doing so poorly. If it's not a Bug and The AMX scales exponentially with Sockets...Well the performance of the 4P parts will be mind-blowing.
 
Hulk

Hulk

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Oct 9, 1999
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Exist50 said:
Looks like many of them are tightly coupled to memory, so probably not possible. Maybe the encryption stuff though?

Training, largely true, but inference is surprisingly dominated by CPUs. The GPU advantage diminishes until tight latency constraints or small batch sizes, and CPUs are obviously more flexible if you're not going to be doing inference all the time.

For training, GPUs are great if your model fits in VRAM (or is amenable to being streamed in), but for really, really large models, they sometimes have to fall back to CPUs.

Jim Keller remarked on this in talk once. I skipped to the relevant part, but the whole thing is worth a watch. Timestamp at 42:47, if the media embed messes it up.


TLDW: He estimated at the time (about 3 years ago) that AI was something like 80% CPU, 20% GPU, 0% other, and says that if things moved quickly, it would be something like 1/3 each in 5 years, but things probably wouldn't move that quickly.
Click to expand...

This is a quite amazing video for people like us that are into this stuff. If you haven't watched it I suggest you do.
Thanks for sharing.
 
DrMrLordX

DrMrLordX

Lifer
Apr 27, 2000
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Henry swagger said:
Impressive outshipping the competition with ease
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That's a lot of people getting stuck with Cascade Lake-SP because nothing else was available. And Cascade Lake-SP was selling at a significant discount. From a revenue and technology point-of-view, that's not really great for Intel.

Exist50 said:
A slight clock penalty isn't meaningful if it only happens when you're running significantly more ops/cycle.
Click to expand...

It is if you're hosting VMs on that system and someone starts up an AVX512 workload on their VM, slowing down the entire host CPU. At least that was a problem with Skylake/Cascade Lake generation CPUs.
 
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Exist50

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Aug 18, 2016
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DrMrLordX said:
It is if you're hosting VMs on that system and someone starts up an AVX512 workload on their VM, slowing down the entire host CPU. At least that was a problem with Skylake/Cascade Lake generation CPUs.
Click to expand...
The clocks are controlled on a per-core granularity. So only the core running heavy AVX512 or AMX code will have a frequency penalty.
 
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IntelUser2000

IntelUser2000

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Oct 14, 2003
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moinmoin said:
Usage of Intel's AVX-512 was known to reduce operating frequency due to higher power consumption, which doesn't happen with AMD's implementation of AVX-512 where AVX-512 is actually using slightly less power than AVX2.
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Icelake-SPs AVX-512 is far better than on Skylake-SP, for obvious reasons like being on the 10nm process.

The big reason AMD's implementation results in less downgrade is because it uses 2 cycles to execute an AVX-512 instruction. Vector instructions take more than 60% of the power use of a core, it makes sense if you increase that, then you need to sacrifice. But if you are getting 2x as much per clock, lowering clock by few % still pays off.
 
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Geddagod

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Dec 28, 2021
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But.. but.. MLID saying Lion Cove was the ground up design?!?!?!
Btw Harukaze quotes that tweet and said that there prob won't be much new, exciting info on the 26th about Lunar Lake, so idk about getting my hopes up too much for any exciting info.
Kind of like how we were supposed to get "more info" about MTL at hotchips, but we didn't get much really at all...
 
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Exist50

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Aug 18, 2016
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Geddagod said:
But.. but.. MLID saying Lion Cove was the ground up design?!?!?!
Btw Harukaze quotes that tweet and said that there prob won't be much new, exciting info on the 26th about Lunar Lake, so idk about getting my hopes up too much for any exciting info.
Kind of like how we were supposed to get "more info" about MTL at hotchips, but we didn't get much really at all...
Click to expand...
Lunar Lake uses Lion Cove. But it's still not Royal.

But agreed. They're not going to seriously discuss LNL till after MTL launches.
 
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IntelUser2000

IntelUser2000

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Oct 14, 2003
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The PC Roadmap seminar that went live today talked about nothing significant. I was hoping for a mobile roadmap leak.

Why do they do this? Just don't talk about it at all. It's like a kid crying and screaming "Please PLEASE PAY ATTENTION TO ME!!"

The real juicy stuff is always hidden behind a veil. Who'd have known without going to Twitter or Anandtech forums?

MJ will probably talk about one more thing in addition to what we already know about Lunar Lake(almost nothing), and we'd have to wait few weeks or even couple of months by a leaked slide to get something real. Since Lunar Lake is few generations away, that leaked slide could be couple of years away.
 
DrMrLordX

DrMrLordX

Lifer
Apr 27, 2000
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IntelUser2000 said:
The PC Roadmap seminar that went live today talked about nothing significant. I was hoping for a mobile roadmap leak.

Why do they do this? Just don't talk about it at all. It's like a kid crying and screaming "Please PLEASE PAY ATTENTION TO ME!!"
Click to expand...

Odd. It seemed urgent when first announced.
 
moinmoin

moinmoin

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Jun 1, 2017
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trivik12 said:
https://twitter.com/x/status/1613732164612554753

You must add personal commentary when dropping links/tweets.

Daveybrat
AT Moderator

Edit: Further details about MTL/ARL/LNL from Intel Client head Michelle Johnston Holthaus.
Click to expand...
"important features (...) like silencing dog barking or lawnmowers"

I'm not sure what to think about this being the only use case mentioned for the upgrades of their chips...
 
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Saylick

Saylick

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Sep 10, 2012
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MTL will be released in 2023, while Lunar Lake will be production ready in 2024 on 18A. Intel's roadmap indicates that 18A is ready for HVM in 2H 2024, so we'll likely see some form of Lunar Lake SKU come out during the 2024 holiday season so that Intel can say they met their timeline goals, even if it's in limited quantities.
 
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