Simulation tools are great for the actual digital logic design on a theoretical level. They are good, but not perfect, at simulating your intended implementation on fully known and modeled silicon implementations where you are absolutely sure about every behavior in every situation. They are often, at best, an educated guess when you are dealing with what is essentially your leading edge silicon in one of it's largest implementations. Silicon is not an exact science with very minute differences in every wafer and chip. What works on 95% of them may not work on that last 5% exactly 100% of the time. Very minor differences in the chemistry of the various layers can make unexpected changes in the timing of signals propagating along a pathway or the behavior of a specific transistor, requiring you to go back and build in additional margin at the silicon level to get your yields to where you want them to be. This is all a vast over-simplification of the process, but, simulation can only go so far, and there's a lot that doesn't get captured at the simulation level for designs that are expected to run at the bleeding edge of capability, 24/7, with effectively zero errors.