Discussion Intel current and future Lakes & Rapids thread

[igor_kavinski]

But my main question is about the CPU images. That looks like 4 P cores (brown) and 4 E cores (blue) which seems like an awfully low core count for Arrow Lake. Is it instead 4 P cores (blue) and 4 blocks of E cores (brown)? If so, then the E core blocks they seem too large in comparison to the P cores. Are they adding something to the E core die size? Or are they having more than just 32 E cores? I'm just speculating here, the image could be non-representative of the actual products.

What if the brown squares are E-core clusters with huge caches? Conversely, what if the small squares are E-cores sharing cache with only two large P-cores and the other two P-cores get to be faster due to not sharing cache? The size disparity indicates huge L2 cache in the brown squares.

 

[jpiniero]

There's no evidence of that. Apple is using N4 for A16 because N3 won't be ready in time. N3E won't be ready in time for A17, so they can either use N3 or do something they've never done and stay with the same process for two straight years with N4.

Could use N4P. Or maybe Samsung??? (ha)

 

[uzzi38]

There's no evidence of that. Apple is using N4 for A16 because N3 won't be ready in time. N3E won't be ready in time for A17, so they can either use N3 or do something they've never done and stay with the same process for two straight years with N4.

N4P is a thing.

 

[Joe NYC]

Or that N3 is craptastic, like I've been saying for a bit now.

Intel are clearly trying to shift products away from TSMC. Arrow Lake was previously rumoured to be only N3. Now it's looking like N3 is for gfx only. Meteor Lake still probably uses N3 for gfx. Sierra Forrest is now pushed back a year and on i3 instead.

Apple are skipping the base N3 for N3E. And AMD likely won't be using base N3 either, but I don't know about Strix Point's node. It's not a good node.

Looks that way. And for Intel iGPU tile, TSMC N5/N4 should have been just fine. Looks like Intel is going to be holding the bag, pre-paying big time for TSMC's most problematic node...

 

[desrever]

Intel still won't be able to fab GPUs internally even on Intel 4. I think that is a much bigger problem than w/e TSMC N3 has. N3 might be been delayed 1Q but theres no reason to think it was a dud. TSMC makes multiple versions of every node depending on customer needs.

 

[IntelUser2000]

Apple are skipping the base N3 for N3E. And AMD likely won't be using base N3 either, but I don't know about Strix Point's node. It's not a good node.

Does it matter whether it's N3 or N3E in this context?

If Samsung isn't doing well, Intel is in trouble, and TSMC is screwing up, then it seems there's no good option.

I thought the troubled node was 5nm.

Looking at the Arrow Lake depiction, it shows 16 x 21 = 336 blocks for the GPU tile. If we assume each block is an execution unit, then that matches fairly well with the rumored 320 execution units for Arrow Lake. That gives them the possibility for a few bad EUs.

But my main question is about the CPU images.

The shapes for Meteorlake is way different than the actual one they have shown a little while ago.

Also it's supposed to be 384 EUs for Arrow Lake.

Why give AMD 2 years to lap the "Mont" cores with Zen 4c? Something is not adding up here...

I was asking you since you talked about 2 year delay, but I get you now.

@uzzi38

Sierra Forest being 2024 isn't much of delay compared to expectations of late 2023. That's just one year from Bergamo. We know less about Sierra Forest than we do about Bergamo.

Also I don't think Intel is planning on using the regular Mont cores, because there was a rumor of the -AP version. That is basically Xeon Phi reincarnated, with heavy vector FP support and HBM2 memory on package.

Then the Mont version in server will be a different beast from the Mont cores in client, just like Atom cores in Phis were way different. That would explain why it takes them longer, aside from the fact that servers generally take longer of course.

 

[jpiniero]

If Samsung isn't doing well, Intel is in trouble, and TSMC is screwing up, then it seems there's no good option.

Screwing up might not be the right statement, but N4P might be reasonably competitive with N3 on power and performance. It'd be still pretty surprising for Apple to not use it for the 2023 iPhone.

 

[eek2121]

Intel still won't be able to fab GPUs internally even on Intel 4. I think that is a much bigger problem than w/e TSMC N3 has. N3 might be been delayed 1Q but theres no reason to think it was a dud. TSMC makes multiple versions of every node depending on customer needs.

That is by choice. Intel states they have enough EUV machines to handle 160 wph. In 2023/2024 this will expand to 190/220 wph from the NXE:3800E and another 150 wph from the EXE:5000. By keeping GPU stuff off Intel fabs, they ensure they have more than enough capacity to compete with AMD.

If the numbers I’ve seen are accurate, they currently have only slightly less than TSMC 7nm total capacity (Intel 118k wpm currently vs. 140k wpmTSMC), and 3-4 times the amount that AMD uses total. Once the new upgrades are in place they will be pushing 275k wpm.

In short, Intel does not have EUV issues.

The intel numbers are from slides provided by Intel for investor day. They are also consistent with the numbers I pulled off ASML’s website. The rest of the numbers came from googling.

 

[semiman]

What happened to Granite Rapids? 2024 seems too late given the fact that AMD is already far ahead. Sapphire Rapids is a great product, but there will be post-Milan products with massive core counts.

 

[jpiniero]

What happened to Granite Rapids? 2024 seems too late given the fact that AMD is already far ahead. Sapphire Rapids is a great product, but there will be post-Milan products with massive core counts.

Retooled because there would be zero chance they would be able to ship it in 2023 anyway.

 

[andermans]

Also I don't think Intel is planning on using the regular Mont cores, because there was a rumor of the -AP version. That is basically Xeon Phi reincarnated, with heavy vector FP support and HBM2 memory on package.

Then the Mont version in server will be a different beast from the Mont cores in client, just like Atom cores in Phis were way different. That would explain why it takes them longer, aside from the fact that servers generally take longer of course.

I thought something like Sierra Forest would be mostly focused on clouds? In that case a heavy FP focus would barely attract customers, so that wouldn't really make sense IMO.

 

[DrMrLordX]

Will NVidia buy Intel to end the misery?

Is Intel's x86 license transferrable?

Intel still won't be able to fab GPUs internally even on Intel 4. I think that is a much bigger problem than w/e TSMC N3 has. N3 might be been delayed 1Q but theres no reason to think it was a dud. TSMC makes multiple versions of every node depending on customer needs.

Considering how many N3 wafers Intel is taking from TSMC, they'd better hope N3 isn't delayed any further.

That is by choice. Intel states they have enough EUV machines to handle 160 wph.

Um. How does that translate into kilowafers per month? Surely Intel doesn't claim that they can produce ~115k kwpm on Intel 4 or Intel 3.

 

[eek2121]

Um. How does that translate into kilowafers per month? Surely Intel doesn't claim that they can produce ~115k kwpm on Intel 4 or Intel 3.

That is certainly what they appear to be saying, since Intel 4 is their first EUV process. They may have capacity issues elsewhere, but not with EUV.

Assuming 8,766 hours in a year at 160 wph that is an average of 116,880 wafers per month.

 

[Joe NYC]

Sierra Forest being 2024 isn't much of delay compared to expectations of late 2023. That's just one year from Bergamo. We know less about Sierra Forest than we do about Bergamo.

Also I don't think Intel is planning on using the regular Mont cores, because there was a rumor of the -AP version. That is basically Xeon Phi reincarnated, with heavy vector FP support and HBM2 memory on package.

Then the Mont version in server will be a different beast from the Mont cores in client, just like Atom cores in Phis were way different. That would explain why it takes them longer, aside from the fact that servers generally take longer of course.

That will always be the case. There will always be a new, better core some years later, with more advanced capabilities.

What I was wondering - why Intel did not think of making the current "Mont" into a product. Intel had a head start in having the core ready in 2021 in Alder Lake. Instead of having 1 year lead against Bergamo, it will trail Bergamo by 2 years, or may even trail Bergamo successor.

not make it (the Mont core) a product, since Intel had the current version ready in 2021 (in Alderlake).

 

[Exist50]

That will always be the case. There will always be a new, better core some years later, with more advanced capabilities.

What I was wondering - why Intel did not think of making the current "Mont" into a product. Intel had a head start in having the core ready in 2021 in Alder Lake. Instead of having 1 year lead against Bergamo, it will trail Bergamo by 2 years, or may even trail Bergamo successor.

not make it (the Mont core) a product, since Intel had the current version ready in 2021 (in Alderlake).

They seem to be having enough trouble with Sapphire Rapids, despite the core being working in Alder Lake, to not want to make matters worse by splitting their efforts with an Atom derivative. Or to put it a little less gently, they need to be able to do anything right before worrying about new categories.

 

[jpiniero]

They seem to be having enough trouble with Sapphire Rapids, despite the core being working in Alder Lake, to not want to make matters worse by splitting their efforts with an Atom derivative. Or to put it a little less gently, they need to be able to do anything right before worrying about new categories.

Sapphire Rapids is a lot of 10 nm silicon, that's the problem.

 

[Markfw]

So you are saying that Sapphire Rapids uses 56 Alder lake cores ? I thought that was the advertised count. If so, they have to be cutting the power WAY back to do anything that can be cooled.

 

[João Bortolace]

sapphire rapids die shot

https://twitter.com/x/status/1495025842988404736

 

[jpiniero]

The IO and the EMIB takes up a ton of space.

 

[Exist50]

Sapphire Rapids is a lot of 10 nm silicon, that's the problem.

No, it's not. They're not delaying it for quarter after quarter because of process yields.

 

[jpiniero]

No, it's not. They're not delaying it for quarter after quarter because of process yields.

Given that Icelake Server's launch was basically last quarter, it sure looks that way.

 

[Exist50]

Given that Icelake Server's launch was basically last quarter, it sure looks that way.

The product that launched with larger dies on a worse process? No, the design side is borked more than process. They couldn't even manage to fully support CXL.

 

[jpiniero]

The product that launched with larger dies on a worse process? No, the design side is borked more than process. They couldn't even manage to fully support CXL.

But you need 4 for the price of 1.

 

[moinmoin]

sapphire rapids die shot

https://twitter.com/x/status/1495025842988404736

Looks like EMIB takes up around 21% of the chip. That's really a lot. Back with Epyc Naples AMD talked about an MCM area overhead of ~10%. For SPR Intel is essentially more than doubling that overhead to offer monolithic-like latency.

 

[IntelUser2000]

That will always be the case. There will always be a new, better core some years later, with more advanced capabilities.

Yes, but the mont cores in Sierra Forest is not going to be the one being used in the mont cores a year after that. The mont cores seem to have a 2 year cadence anyways.

Just like the 14nm Xeon Phi's core wasn't Airmont, but Silvermont.

Server always takes longer and there's that too.

I thought something like Sierra Forest would be mostly focused on clouds? In that case a heavy FP focus would barely attract customers, so that wouldn't really make sense IMO.

Rumors and leaks both point to Sierra Forest AP. We'll see what they do there.

Also being on the future process they can probably do something like 256-bit FP paths but AVX-512 support as in the client P cores.