Discussion Intel current and future Lakes & Rapids thread

[DrMrLordX]

I mean it should be pretty obvious. Until they manage to have enough capacity to produce enough chips on Intel 4 (with EUV) on their own they will co-source.

Yeah, but which product will use N4? Something in the Arc lineup? Arrow Lake?

 

[SAAA]

He said, instead of 15% IPC increase on average, he expects that there will be a single large IPC jump, the rest will be much smaller jumps. That means something like this for example.

	Alder Lake	Raptor Lake	Meteor Lake	Arrow Lake	Lunar Lake	Nova Lake
IPC	100​	108(+8%)	122(+13%)	134(+10%)	144(+7.5%)	200(+39%)

* I think 15% on average is more believable than 39% increase in a single generation Only my opinion.

Honestly with their strategy being double and quadruple down on little cores pushing IPC to the max on the big ones like this doesn't sound impossible. A welcome target for sure.
There's also quite a few nodes in between so keeping count at 8 will leave a lot of transistors to play with, hopefully they can look at efficiency too and not stray much further from Alder's TDPs.

Also don't forget twice the IPC doesn't necessarily mean it will run at the same 5-5.5 GHz like Alder or Raptor, I'd be much happier to see 4-4.5 GHz again to reset voltages and temps a bit.
But that mostly depends on competition and how much of a factory OC they'll want to push for.

 

[repoman27]

Yeah, but which product will use N4? Something in the Arc lineup? Arrow Lake?

Meteor Lake SoC tile is rumored to be TSMC N5P or N4. Which would slot in for H2'22, after Apple is done making a bajillion A16's and M2's.

Some other thoughts...

Intel isn't going to tape out the same die on both internal and external processes. Apple multi-sourced once, with the A9, but Intel doesn't make anything with close to that kind of volume. Furthermore, Intel probably doesn't want any direct compares between their processes and TSMC's available in the wild. Samsung 14LPE and TSMC 16FF were also much closer to one another than anything from Intel and TSMC at the moment.

Historically, Intel has averaged 7 tape outs per year to produce all of their Core client platforms (4-6 CPU plus 2 PCH). From both engineering resources and financial standpoints, I don't see them committing to doing significantly more than that going forward. As they shift to tile based designs, individual platforms will require a greater number of tape outs. Intel will have to reuse tiles across the product stack in order to avoid significantly increasing the number of unique dies they need to produce and provide sufficient volume to justify the design and mask costs. Meteor Lake will probably require at least two different Foveros base tiles (LP and HP), two compute tiles (4+8 and 6+8), two SoC tiles (LP and HP), and one GPU tile (128 EU). That's sort of the whole wad right there. Lunar Lake might be another full stack like MTL, but Arrow Lake may only require new base and SoC tiles while utilizing GPU tiles from MTL and CPU tiles from LNL.

 

[Saylick]

From what I’ve heard, Royal core is about offering the efficiency of the Atom line up whilst also maintaining the performance of the Core line-up, through clever engineering and trickery.

Intels acquisition of SoftMachines back in 2016 offers a MASSIVE hint of how this is achievable.

Oh no, not the VISC architecture again. If I'm not mistaking what you're implying, this means that Intel wants to virtualize a process over multiple Next Mont cores to create a virtual big core out of many small cores. I'll have to go back and dig through the thread that was created when this VISC/"reverse hyperthreading" concept was discussed, but there were a lot of skeptics, and for good reason.

 

[igor_kavinski]

Oh no, not the VISC architecture again. If I'm not mistaking what you're implying, this means that Intel wants to virtualize a process over multiple Next Mont cores to create a virtual big core out of many small cores. I'll have to go back and dig through the thread that was created when this VISC/"reverse hyperthreading" concept was discussed, but there were a lot of skeptics, and for good reason.

Intel paid good money for the technology so it must work. They just need to adapt it to x86. Their best bet is designing their monts around it.

 

[Exist50]

Honestly with their strategy being double and quadruple down on little cores pushing IPC to the max on the big ones like this doesn't sound impossible. A welcome target for sure.
There's also quite a few nodes in between so keeping count at 8 will leave a lot of transistors to play with, hopefully they can look at efficiency too and not stray much further from Alder's TDPs.

Also don't forget twice the IPC doesn't necessarily mean it will run at the same 5-5.5 GHz like Alder or Raptor, I'd be much happier to see 4-4.5 GHz again to reset voltages and temps a bit.
But that mostly depends on competition and how much of a factory OC they'll want to push for.

I find it pretty funny that 2x GLC IPC is unfathomable to some when today, Apple already has 2x Skylake IPC in a core suitable for cell phones. They'll probably hit 2x GLC in a year or two.

Intel paid good money for the technology so it must work. They just need to adapt it to x86. Their best bet is designing their monts around it.

I'm not so sure. Intel's got a poor tract record with leveraging acquisitions. Not dismissing the possibility, but I don't think it's a given that we'll see anything.

 

[IntelUser2000]

Well the rumor mills are saying Arrow and Lunar both having same cores, so the big jump has to be coming from Arrow, at least on the perf/clock side and big one again with Nova.

I wonder if Crestmont in Meteor will be a big E core jump, or if they are moving to smaller yearly jumps since Arrow will have Skymont?

 

[dullard]

Well the rumor mills are saying Arrow and Lunar both having same cores, so the big jump has to be coming from Arrow, at least on the perf/clock side and big one again with Nova.

If you believe Curmudgeon666, then we get https://forums.anandtech.com/thread...ure-lakes-rapids-thread.2509080/post-40551904

• 10% with Raptor Lake
• Single digit gain with Meteor Lake
• Unspecified gain with Arrow Lake
• Big gain with Lunar Lake
• 50% gain with Nova Lake

Suppose that Meteor Lake single digit gain was ~9%, we'd then end up with Intel's claimed 20% performance/watt gain with Intel 4. Yes, performance/watt is not the same as IPC, but assuming the power levels are close then they are not that far apart, and it is the only concrete information we have to go on at this point. By Intel 3 we have another 18% gain in performance per watt. So, Arrow Lake and Lunar Lake together will get about 18% IPC gain (again, I know IPC and performance/watt are not the same thing). Going with Curmudgeon666's big gain with Lunar Lake, it means the Arrow Lake gain would be small. Not knowing how small, I'll just assume 5% with Arrow Lake and 12% with Lunar Lake.

With all those assumptions you get:

	Alder Lake	Raptor Lake	Meteor Lake	Arrow Lake	Lunar Lake
IPC	100	110 (+10%)	120 (+9%)	126 (+5%)	141 (+12%)

The 50% gain with Nova Lake seems the least likely. Intel does claim to have two breakthrough innovations with RibbonFET and PowerVia, but I'm not sure that would actually translate into IPC. More likely it might just let higher frequencies be possible with performance from higher clocks not necessarily from IPC. Not having anything to really go on, I'd think 30% jump is far more likely than 50% claimed by Curmudgeon666. That would put Nova at an ~83% gain over Alder Lake.

 

[IntelUser2000]

If you believe Curmudgeon666, then we get https://forums.anandtech.com/thread...ure-lakes-rapids-thread.2509080/post-40551904

I'd go far as believing him being correct in a general sense(Intel's expectations) but I wouldn't take details(such TSMC 3nm) at a face value.

Actually regarding Intel data the youtuber MLID is starting to gain credibility.

Again either Arrow and Lunar use two very different core uarchs or the gains between them will be entirely perf/watt or perf/mm2 and pef/clock difference = 0. They are the same core. It's like saying Coffeelake is much faster than Skylake, when in reality they are identical.

The 50% gain with Nova Lake seems the least likely. Intel does claim to have two breakthrough innovations with RibbonFET and PowerVia, but I'm not sure that would actually translate into IPC.

Usually a "breakthrough" means it allows "advancements to continue" rather than "astounding gains". Without it the gains quickly go to zero.

After the breakthrough called FinFET we got lower gains and situational gains.

The work is getting harder but you are getting paid less.

 

[Exist50]

If you believe Curmudgeon666, then we get https://forums.anandtech.com/thread...ure-lakes-rapids-thread.2509080/post-40551904

• 10% with Raptor Lake
• Single digit gain with Meteor Lake
• Unspecified gain with Arrow Lake
• Big gain with Lunar Lake
• 50% gain with Nova Lake

Suppose that Meteor Lake single digit gain was ~9%, we'd then end up with Intel's claimed 20% performance/watt gain with Intel 4. Yes, performance/watt is not the same as IPC, but assuming the power levels are close then they are not that far apart, and it is the only concrete information we have to go on at this point. By Intel 3 we have another 18% gain in performance per watt. So, Arrow Lake and Lunar Lake together will get about 18% IPC gain (again, I know IPC and performance/watt are not the same thing). Going with Curmudgeon666's big gain with Lunar Lake, it means the Arrow Lake gain would be small. Not knowing how small, I'll just assume 5% with Arrow Lake and 12% with Lunar Lake.

With all those assumptions you get:

	Alder Lake	Raptor Lake	Meteor Lake	Arrow Lake	Lunar Lake
IPC	100	110 (+10%)	120 (+9%)	126 (+5%)	141 (+12%)

The 50% gain with Nova Lake seems the least likely. Intel does claim to have two breakthrough innovations with RibbonFET and PowerVia, but I'm not sure that would actually translate into IPC. More likely it might just let higher frequencies be possible with performance from higher clocks not necessarily from IPC. Not having anything to really go on, I'd think 30% jump is far more likely than 50% claimed by Curmudgeon666. That would put Nova at an ~83% gain over Alder Lake.

Just FYI, Curmudgeon666 was quoting a reddit post by user mooreslawisnotdead.

In any case, the predictions/commentary are about performance gains, not IPC. Will probably make it difficult to draw any substantial conclusions without further info.

 

[mikk]

Well the rumor mills are saying Arrow and Lunar both having same cores, so the big jump has to be coming from Arrow, at least on the perf/clock side and big one again with Nova.

I wonder if Crestmont in Meteor will be a big E core jump, or if they are moving to smaller yearly jumps since Arrow will have Skymont?

You have to assume that the reddit leak is accurate in this regards. I believe it is not, I believe Arrow is some sort of a Meteor refreh on a different node and with a core count increase both CPU and GPU. Arrow was not present in the driver leak late 2020, only Meteor and Lunar. I think Intel realized Meteor Lake-S is not working for desktop and they use Arrow instead as a stopgap for the desktop and higher end mobile.

Furthermore the reddit leak doesn't imply Arrow is a big tock architecture upgrade, he says it's a tile upgrade to 8+32 for the highend which makes sense. Then for Lunar he expects a big performance jump. Doesn't make sense to me if there are no IPC gains over Arrow. I think Lunar is the tock architecture upgrade.

The other thing is Intel changed the Cove nomenclature for Rocketlake just because it's on a different node. Cypress Cove and Sunny Cove is on the same architecture, just on a different process. So if Lunar is on a different process, on a TSMC process reportedly according to him, it doesn't make sense to me that the Cove+Mont code names are exactly the same even if it's the same architecture as Arrow. I think the same Cove+Mont is a mistake from the reddit poster. Maybe Meteor and Arrow is the same and he just made an error there.

The 50% gain with Nova Lake seems the least likely. Intel does claim to have two breakthrough innovations with RibbonFET and PowerVia, but I'm not sure that would actually translate into IPC. More likely it might just let higher frequencies be possible with performance from higher clocks not necessarily from IPC. Not having anything to really go on, I'd think 30% jump is far more likely than 50% claimed by Curmudgeon666. That would put Nova at an ~83% gain over Alder Lake.

The last Finfet generation change from 2d to 3d wasn't about higher frequencies, actually the clock speeds were reduced from 32nm to 22nm. It's not directly about IPC of course, it's more about power and transistor savings. They can put much more transistors into a new architecture which as a result can be used for IPC improvements. If Nova Lake is really something completely new from the ground up there is a chance the IPC gains are abnormal high for once. Examples are NetBurst to Core or Bulldozer to Zen.

 

[dullard]

The last Finfet generation change from 2d to 3d wasn't about higher frequencies, actually the clock speeds were reduced from 32nm to 22nm. It's not directly about IPC of course, it's more about power and transistor savings. They can put much more transistors into a new architecture which as a result can be used for IPC improvements. If Nova Lake is really something completely new from the ground up there is a chance the IPC gains are abnormal high for once. Examples are NetBurst to Core or Bulldozer to Zen.

The changes are both about higher frequencies and more room for more transistors.

• RibbonFET is being described by Intel as (1) faster transistor switching speeds for higher performance and (2) smaller footprint for more transistors.

• PowerVias being described by Intel as giving a "significant frequency boost"

What we don't know is how much Intel will be going for IPC with more transistors vs. how much Intel will be going just for higher frequencies.

 

[lobz]

15% every generation is not out of reach. I believe we will see more than 15% with Lunar and a lot more with Nova. Meteor might be less than 15% and Raptor most likely as well. Intel can invest in more P core size+performance because the P core count increase is on hold thanks to the E cores. And there is big competition with AMD, I think we will see bigger IPC increases the next few years.

I guess we'll have to wait and see.

 

[Hulk]

I hope I'm wrong but I predict Golden Cove will be the new Skylake, meaning with minor changes to memory subsystem, process, move to tiles, it will remain the same basic microarchitecture for years. I also think AMD will essentially do the same thing with Zen 3. There will be a unsaid truce between AMD and Intel as they make tremendous profits.

 

[dullard]

There will be a unsaid truce between AMD and Intel as they make tremendous profits.

You can't have a truce without a fight. Intel and AMD are on the same team: them vs ARM.

 

[lobz]

From what I’ve heard, Royal core is about offering the efficiency of the Atom line up whilst also maintaining the performance of the Core line-up, through clever engineering and trickery.

Intels acquisition of SoftMachines back in 2016 offers a MASSIVE hint of how this is achievable.

Hopefully to a more effective extent than AMD's purchase of ATI.

 

[gdansk]

Apple is way ahead in IPC. If that "lifestyle company" memo was any indication then Intel is targeting high IPC. Apple having 2x IPC of present Intel CPUs by late 2025 doesn't seem impossible. Even if they're confident Apple won't be willing to clock as high, Intel need massive increases. 1.5x at least.

 

[Hougy]

Apple is way ahead in IPC. If that "lifestyle company" memo was any indication then Intel is targeting high IPC. Apple having 2x IPC of present Intel CPUs by late 2025 doesn't seem impossible. Even if they're confident Apple won't be willing to clock as high, Intel need massive increases. 1.5x at least.

They could reach 2x IPC if they start designing much lower frequency chips with fewer pipeline stages using a higher density process

 

[eek2121]

They could reach 2x IPC if they start designing much lower frequency chips with fewer pipeline stages using a higher density process

They won’t, they are addicted to 5+ ghz.

 

[mikk]

I hope I'm wrong but I predict Golden Cove will be the new Skylake, meaning with minor changes to memory subsystem, process, move to tiles, it will remain the same basic microarchitecture for years. I also think AMD will essentially do the same thing with Zen 3. There will be a unsaid truce between AMD and Intel as they make tremendous profits.

Same Cove for years, no way. Intel had to refresh Skylake architecture for several generations because of their process issues. We will se bigger changes on both sides the next years.

 

[Hulk]

Same Cove for years, no way. Intel had to refresh Skylake architecture for several generations because of their process issues. We will se bigger changes on both sides the next years.

Great. I will be happy to be dead wrong on this one. It will be interesting to see how wide and smart these cores can become.

 

[Hulk]

You can't have a truce without a fight. Intel and AMD are on the same team: them vs ARM.

True. "Quiet agreement" would be a better term.

 

[Khato]

Regarding ARL vs LNL performance expectations according to the reddit post that Curmudgeon666 captured. One key point on the description of ARL would be the leading sentence, "Will feature an updated compute tile." If you take this to literally mean that ARL is the MTL design with just the compute tile swapped the performance projections make a bit more sense. It would by far be the fastest option for Intel to get the new core design to market, but it could leave a fair bit of performance on the table for LNL to extract. (In addition to the process node advantage for LNL, of course.)

 

[Exist50]

They won’t, they are addicted to 5+ ghz.

Is Intel, or is Core? Will be interesting to see which.

 

[andermans]

Regarding ARL vs LNL performance expectations according to the reddit post that Curmudgeon666 captured. One key point on the description of ARL would be the leading sentence, "Will feature an updated compute tile." If you take this to literally mean that ARL is the MTL design with just the compute tile swapped the performance projections make a bit more sense. It would by far be the fastest option for Intel to get the new core design to market, but it could leave a fair bit of performance on the table for LNL to extract. (In addition to the process node advantage for LNL, of course.)

I wonder what that would mean for the 384 EU iGPU leaks for ARL. Would the iGPU be in the compute tile?