Discussion Intel current and future Lakes & Rapids thread

[Mopetar]

If you look closely at the specs, you'll see Intel is artificially segmenting things. There does not seem to be much in the way of actual defects. Note that I'm not saying Intel won't have defects, just that if they did (have a lot of defects), you'd see SKUs that are a bit more finer grained.

EDIT: clicked save too soon.

Defects aren't the only reason to bin chips and disable hardware.

If they are trying to push the frequency on those e-cores there will be cases where not all of them can reach that performance target. So they disable a cluster in that case.

I have no insider knowledge of the answer. But my main question is why Intel didn't go for 6+16 or 4+24 right away.

Amdahl's law.

For desktop users most workloads aren't highly parallel such that 24 cores is beneficial. Since Intel is making a single die that covers all the different products they can't cover the niche users that would see a lot of benefit from 24 small cores over the added big cores.

 

[Hulk]

I don't know a lot about what makes a good server architecture but from what I do know it seems like lots of power efficient cores are useful.

Why is Intel focusing on 40+ Golden Cove cores for SR instead of 160+ cores in the same die space using Gracemont? Just to be clear I'm not saying they should, this is above my pay grade but I know many here will have some solid reasoning for their decision to focus on Golden Cove for SR.

 

[dullard]

Why is Intel focusing on 40+ Golden Cove cores for SR instead of 160+ cores in the same die space using Gracemont? Just to be clear I'm not saying they should, this is above my pay grade but I know many here will have some solid reasoning for their decision to focus on Golden Cove for SR.

AVX-512 would be my guess.

 

[Exist50]

Since Intel is making a single die that covers all the different products they can't cover the niche users that would see a lot of benefit from 24 small cores over the added big cores.

They're not making just one die.

As for why Gracemont seem to be more disabled, I'd wager it has more to do with product segmentation than anything else.

 

[jpiniero]

Intel to launch 12th Gen Core Alder Lake-S and Z690 motherboards on November 19th - VideoCardz.com

Intel Alder Lake has a release date According to Wccftech, who are quoting their own sources, Intel is expected to launch its Alder Lake-S CPUs on November 19th. Intel Alder Lake Engineering Sample, Source: HKEPC The site claims that the product launch will not take place at the same time as the...

videocardz.com

Looks like the actual release date of Alder Lake is possibly November 19th.

 

[Hulk]

They're not making just one die.

As for why Gracemont seem to be more disabled, I'd wager it has more to do with product segmentation than anything else.

Three dies, but only one is for the desktop.

 

[Exist50]

Three dies, but only one is for the desktop.

4 dies, with 2 being for desktop. Both 8+8 and 6+0.

 

[Hulk]

4 dies, with 2 being for desktop. Both 8+8 and 6+0.

Anandtech article described 3, Desktop, Mobile, and Ultra Mobile. Where did you get the info for the four dies? Makes sense.

 

[Exist50]

Anandtech article described 3, Desktop, Mobile, and Ultra Mobile. Where did you get the info for the four dies? Makes sense.

Been pretty consistently leaked. Expect it to be used for locked i5s and below. Can't just throw an 8+8 die into i3s.

 

[Saylick]

I don't know a lot about what makes a good server architecture but from what I do know it seems like lots of power efficient cores are useful.

Why is Intel focusing on 40+ Golden Cove cores for SR instead of 160+ cores in the same die space using Gracemont? Just to be clear I'm not saying they should, this is above my pay grade but I know many here will have some solid reasoning for their decision to focus on Golden Cove for SR.

I believe there's rumors of a high core count Gracemont-based server part. Forgot what it's called though.

As for why make a server part out of the Big Core only, it's because single threaded performance still matters in server workloads, plus there's a lot of special instructions that the Big Core can run that the Small Core can't.

 

[mikk]

Intel to launch 12th Gen Core Alder Lake-S and Z690 motherboards on November 19th - VideoCardz.com

Intel Alder Lake has a release date According to Wccftech, who are quoting their own sources, Intel is expected to launch its Alder Lake-S CPUs on November 19th. Intel Alder Lake Engineering Sample, Source: HKEPC The site claims that the product launch will not take place at the same time as the...

videocardz.com

Looks like the actual release date of Alder Lake is possibly November 19th.

And a pre-launch announcement in late October with performance numbers, specifications and prices. This is like a paper launch.

 

[IntelUser2000]

Defects aren't the only reason to bin chips and disable hardware.

If they are trying to push the frequency on those e-cores there will be cases where not all of them can reach that performance target. So they disable a cluster in that case.

Actually there is a reason to disable cores and the reason being not have to do with defects or the inability to reach a certain frequency.

Why do they disable the gracemont clusters? Because it gives them a reason to sell it at a lower price.

Would it make sense to only sell 8+8 Alderlake but at different price points? No. Or would it make sense to sell only $300+ Alderlake chips? Certain part of the market will only accept up to a certain price point.

So purposely disabling them to sell it at a lower price makes sense from a financial point of view since silicon costs are under $20.

 

[DrMrLordX]

I think the reason for 8+8 is gaming and maybe marketing.

No, it's because of actual performance. See below.

Amdahl's law.

For desktop users most workloads aren't highly parallel such that 24 cores is beneficial. Since Intel is making a single die that covers all the different products they can't cover the niche users that would see a lot of benefit from 24 small cores over the added big cores.

Thank you! Lots of Gracemont cores won't fill most people's computational needs. AMD has already pushed the envelope on "moar coars" to the limits of absurdity. For many users, more than 8c doesn't make a lot of sense right now. Like it or not, Golden Cove is the most-performant core Intel can pack into a CPU. They may be area-and-power inefficient, but they will put up the numbers to compete in some benchmarks. The true oddity is why Intel feels it's beneficial to have an 8c Gracemont cluster connected over a link of unknown bandwidth/latency that requires enormously complicated scheduler modifications and other shenanigans merely to justify its existence. A healthier Intel would have a seperate lineup of Atom products in various core configurations for people "who want that sort of thing" and to incentivize their Atom team to eventually supplant Core with Atom, perhaps a generation or two from now assuming Atom can continue with +20-30% IPC gains generation-over-generation. The Intel that we have instead has shlepped out a Golden Cove so massive and inefficient that they can't compete on core count with AMD. They feel compelled to include Gracemont to take a shot at MT workloads.

AVX-512 would be my guess.

Intel had plans for a variant of Tremont with Phi-like implementation of AVX-512 and SMT4. It's reasonable to conclude that, if they wanted to, a similar Gracemont-derived core connected to a mesh would be possible. But they would have to really want to sell that product. Officially, Intel killed all that around the time they launched Cascade Lake-AP.

I believe there's rumors of a high core count Gracemont-based server part. Forgot what it's called though.

Right now they're selling higher-core-count Tremont in various network and communications roles. Sort of a narrower role than that assigned to Denverton. If they wanted, high-core-count Gracemonth could attempt to truly supplant Denverton or maybe even sell it as a Xeon-D product.

 

[IntelUser2000]

Intel had plans for a variant of Tremont with Phi-like implementation of AVX-512 and SMT4. It's reasonable to conclude that, if they wanted to, a similar Gracemont-derived core connected to a mesh would be possible. But they would have to really want to sell that product. Officially, Intel killed all that around the time they launched Cascade Lake-AP.

Phi-like implementation? Aren't you talking about the 10nm Xeon Phi? It was cancelled because 10nm was delayed. The 10nm Phi is a Goldmont derivative while the predecessor was Silvermont derivative.

 

[DrMrLordX]

Phi-like implementation? Aren't you talking about the 10nm Xeon Phi? It was cancelled because 10nm was delayed. The 10nm Phi is a Goldmont derivative while the predecessor was Silvermont derivative.

Yes, and yes, though my impression that the final gen of Phi (that was cancelled) was to be Tremont? Well point still stands, Intel knows how to strap AVX-512 and SMT4 onto an Atom core if they have to.

 

[TESKATLIPOKA]

No, it's because of actual performance. See below.

And gaming is about what If not actual performance? No one would buy a 4+16 config over 8+8 or just pure 8 Golden Coves for gaming.
Even If I mentioned only just gaming and didn't explicitly mention 1-8 threaded soft or benches, I still meant the same thing like you.
Golden Cove even with Its disadvantages is still a lot faster than Gracemont, and It's pointless to exchange It for more Gracemont cores when most users don't need more than 8-12 threads.

I think the main reason for 2+8 in mobile is that the limited TDP(<=15W) decreased a lot the performance difference between the two cores. Golden Cove still has a lot higher IPC, but Gracemont can probably clock higher within a limited power budget, so the actual difference is not that big.

 

[IntelUser2000]

Goldmont Plus didn't exist back then nevermind Tremont in the original timeline they wanted 10nm.

I think the main reason for 2+8 in mobile is that the limited TDP(<=15W) decreased a lot the performance difference between the two cores. Golden Cove still has a lot higher IPC, but Gracemont can probably clock higher within a limited power budget, so the actual difference is not that big.

In mobile it's probably even more binary for ST vs. MT split. So with desktops there's a lot of middle ground between the two. But 2+8 means you can maximize the ST and responsiveness portion and the few times you need MT which are likely embarassingly parallel the +8 far outstrips +2 Golden cores.

We'll see how well it does. I think overall it might be pretty good, but there will be overheads and the equation won't be 8+8 but end up 7+7 or 6+6.

 

[DrMrLordX]

And gaming is about what If not actual performance?

It's only one workload that benefits from high IPC and high frequency over core count. There are others. Not all workloads scale with cores count. You can argue about what is the "sweet spot" for total core count, but it should be obvious that consumers would not benefit as much from 8 extra Gracemont cores as they would two Golden Cove.

Even If I mentioned only just gaming and didn't explicitly mention 1-8 threaded soft or benches, I still meant the same thing like you.

Fair enough. It wasn't clear from your statements though. The decision to rely heavily on Golden Cove is no mere marketing gimmick. It's the best Intel has to offer at this time.

Goldmont Plus didn't exist back then nevermind Tremont in the original timeline they wanted 10nm.

Hmm, I thought Tremont would have been ready by 2018 or 2019?

 

[Hulk]

You can argue about what is the "sweet spot" for total core count, but it should be obvious that consumers would not benefit as much from 8 extra Gracemont cores as they would two Golden Cove.

If a particular application is going to scale well from 8 to 10 cores wouldn't it most likely also scale well from 8 to 16 cores, and then in that case might not 8+8 be more beneficial than 10 P's?

 

[insertcarehere]

It's only one workload that benefits from high IPC and high frequency over core count. There are others. Not all workloads scale with cores count. You can argue about what is the "sweet spot" for total core count, but it should be obvious that consumers would not benefit as much from 8 extra Gracemont cores as they would two Golden Cove.

How is it obvious to consumers that 10 GC > 8 GC + 8 GM? The types of workloads that would benefit from the former necessarily have to scale well to 10 cores/20 Threads (otherwise what's the point of 10 GC vs 8 GC that would clock higher in the same PL2), but at the same time, fall off hard when scaling to 16 cores/24 threads, are there somehow lots of consumer software that fit this specific description?

 

[Abwx]

But 2+8 means you can maximize the ST and responsiveness portion and the few times you need MT which are likely embarassingly parallel the +8 far outstrips +2 Golden cores.

We'll see how well it does. I think overall it might be pretty good, but there will be overheads and the equation won't be 8+8 but end up 7+7 or 6+6.

Bulldozer revisited in some way.

Overall i m doubtfull of the concept since low power at high efficency in mobile would require only 2-4 cores for basical tasks that use low average throughput.

Beside a GC core clocked 40% lower than a GRMT would provide same ST perf and better throughput with SMT while consuming comparable power.

Only advantage is marketing since they can advertise a big core amount at lowish die area cost.

 

[Mopetar]

Why is Intel focusing on 40+ Golden Cove cores for SR instead of 160+ cores in the same die space using Gracemont? Just to be clear I'm not saying they should, this is above my pay grade but I know many here will have some solid reasoning for their decision to focus on Golden Cove for SR.

Im sure they're working on it, but it may be that they're still working on that chip. If they want arbitrary cores in such a chip to be able to communicate effectively it's a lot harder to do that when you have 160 cores than when you have 16 or 24.

Another reason is that such a product, while useful, is also going to fill a particular market niche. Some server software charges on a per core basis which means that having a lot of small, efficient, but less powerful cores isn't as beneficial as fewer, but more powerful cores.

Actually there is a reason to disable cores and the reason being not have to do with defects or the inability to reach a certain frequency.

Why do they disable the gracemont clusters? Because it gives them a reason to sell it at a lower price.

If they've saturated every level above that then yes they would do it just to create artificial market segmentation. I think that's more likely later on in the products life though since when they launch they'll have short supply and even if the yields are exceptionally good, they can always make the bins more aggressive until they get the kind of product mix that they want.

To draw a parallel consider Zen 3 right now where AMD hasn't released anything below the 5600. Eventually they'll put out some 4-core part for dirt cheap, but it's unlikely they get many chiplets that naturally need to be binned that way. Once the rest of the market is saturated they can start disabling more cores because they couldn't sell it as a 5600 so may as well try to make a buck on a lower end model.

 

[TESKATLIPOKA]

Beside a GC core clocked 40% lower than a GRMT would provide same ST perf and better throughput with SMT while consuming comparable power.

Only advantage is marketing since they can advertise a big core amount at lowish die area cost.

GC having 40% lower frequency and the same ST perf would mean It has 67% higher IPC than GRMT and I highly doubt that.

2.4GHz GC 1C2T should consume less than GRMT 1C1T at 4GHz with comparable or a bit better performance.
The question is if It's also true for lower clocks like GC: 1.6-2GHz vs GRMT: 2.7-3.3GHz.

 

[LightningZ71]

Remember, it's not just a power tradeoff, it's a die area trade off as well. Yes, GC should be capable of higher IPC at a given clock speed, but it takes roughly 4x the die area. In that same area, in the same power envelope, you can get more work done with a 4x Mont cluster than one cove core with HT.

 

[TESKATLIPOKA]

Yes, but you also need a soft capable of using all those threads.