Discussion Intel current and future Lakes & Rapids thread

[uzzi38]

I personally don’t consider the chip to be a power hog for what it is. The top end SKU has a 350W TDP.

Now more specifically in regards to this, but sorry, no SPR is almost certainly a power hog. 350W for similar or slightly better performance than the 20% lower power consumption Milan is not a great place to be in for a product that costs so much more to produce and almost certainly to buy as well.

PCIe5 and DDR5 are already very expensive, but we're also talking about ~1600mm^2 of 10nm put together with (albeit relatively cheap compared to other advanced packaging technologies) EMIB is not going to be cheap at all. SPR really needs a very solid win performance-wise over Milan to be worth it both for consumers and for Intel.

All these little bits and pieces add up when considering the value of a product. You already have more expensive technologies, but then you're also having to tack on additional power consumption costs as well?

On it's own, power consumption is far from a deal-breaker, so in that sense I agree with you. It's at least ok for the performance in question here. But it's just another thing that adds onto an already kinda long list of small issues that SPR has to deal with.

 

[coercitiv]

Personally I can't wait to see ADL-S pitted versus SPR-X, assuming Intel's HEDT line will get an upgrade within a reasonable time frame. I'll be very curious to see how the lowest HEDT SKU performs against ADL 8+8.

 

[RTX]

Personally I can't wait to see ADL-S pitted versus SPR-X, assuming Intel's HEDT line will get an upgrade within a reasonable time frame. I'll be very curious to see how the lowest HEDT SKU performs against ADL 8+8.

What's the likelihood of both Goldencove based product lines released within 3 months of each other. Skylake was separated by 24 months.

 

[scannall]

Of course nobody ever hypes AMD, right? Or turns Intel threads into AMD ones??

The Hype Train has stations all over the place. Not just Intel and AMD. Game consoles, cars, audio equipment, cameras and just about everywhere else as well.

 

[uzzi38]

What's the likelihood of both Goldencove based product lines released within 3 months of each other. Skylake was separated by 24 months.

Actually quite high, but depends on what you believe constitutes a 'launch'.

 

[Gideon]

IMO much more important than the exact performance of Sapphire Rapid itself, or even it's cost, is how much can Intel actually produce in 2022?
If Intel can shove out enough to satisfy the majority of their server sales in 2022 it would be fine. But considering the complex packaging (at least EMIB), surprisingly big dies, it certainly doesn't seem obvious.

If they still need to leave most of their mid- and lower end lineup to Ice Lake SP, it's already troublesome as even Rome can compete with it in most workloads, let alone Milan. If they also need to move any serious volume of Skylake (I certainly hope not) it will be really bad. That would mean that AMD still sell a truckload of Milan/Rome even while selling all of th Genoas they can produce.

Considering Ice-Lake SP still almost isn't available to anyone but hyperscalers has me a bit worried.

There is no doubt that Sapphire Rapid will have it's niche. A halo 56 core product with HBM2 and DDR5 will do great in bandwidth constraint workloads having gigabytes of poorly cachable data. They will also win all of the I/O bound workloads by default.
But while it will make some benchmark charts look good, if Sapphire Rapid is only, say, 20% of the entire Inte'ls server volume, it won't even stop the bleeding.

 

[uzzi38]

IMO much more important than the exact performance of Sapphire Rapid itself, or even it's cost, is how much can Intel actually produce in 2022?
If Intel can produce enough to satisfy the majority of their server sales 2022 should end up much better than 2021 for them. But with the more complex packaging, actually rather big dies etc, it certainly isn't set in stone.

If they need to leave most of their mid- and lower end lineup to Ice Lake SP it's already trouble as even Rome can compete with it in a number of workloads, let alone Milan (and Milan with V-cache). If they still have to sell Skylake in any serious volume (I certainly hope not) it wills be really bad.

So all in all, while the 56-core Halo product with the HBM2 and DDR5 would make the benchmark charts look good, it would not really help them all that much, if the majority of their sales are Ice-Lake, vs V-cached MIlan, next gen Ampere, etc ...

Judging by the fact that DDR5 shipping volumes aren't expected to overtake DDR4 shipping volumes until mid 2023, I think it's very safe to say that the combination of ADL and SPR won't be overtaking the volume of DDR4 based products in 2022.

 

[Gideon]

Judging by the fact that DDR5 shipping volumes aren't expected to overtake DDR4 shipping volumes until mid 2023, I think it's very safe to say that the combination of ADL and SPR won't be overtaking the volume of DDR4 based products in 2022.

Yeah, I was pretty sure it won't be the case considering the packaging and the fab capability for ESF alone. The lack of DDR5 makes it even more likely.

We shall see I guess, but even if Intel will keep most of their market share, there is no way their margins won't take a hit.

 

[yuri69]

IMO much more important than the exact performance of Sapphire Rapid itself, or even it's cost, is how much can Intel actually produce in 2022?
If Intel can shove out enough to satisfy the majority of their server sales in 2022 it would be fine. But considering the complex packaging (at least EMIB), surprisingly big dies, it certainly doesn't seem obvious.

If they still need to leave most of their mid- and lower end lineup to Ice Lake SP, it's already troublesome as even Rome can compete with it in most workloads, let alone Milan. If they also need to move any serious volume of Skylake (I certainly hope not) it will be really bad. That would mean that AMD still sell a truckload of Milan/Rome even while selling all of th Genoas they can produce.

Technical superiority is one thing but market force is a thing too. Server == Xeon. Right?

Intel would happily keep selling the current Cascade Lakes on dirt cheap 14nm for current prices, wouldn't they?

 

[scineram]

Yeah, it's 15 core tiles per die. Yuuki-ans has confirmed this over Twitter as well already

Nemes has seen the die shots already, he's probably annotating now. Hopefully won't be too long

So why not 16 cores? Looks like a 4x4 grid. What happened to one of the slots?

 

[Saylick]

So why not 16 cores? Looks like a 4x4 grid. What happened to one of the slots?

One of the slots is taken up by the memory controller, e.g. like how it is for their other mesh-based architectures:

 

[yuri69]

So why not 16 cores? Looks like a 4x4 grid. What happened to one of the slots?

You can see Skylake's "IMC tiles" looking distinctive compared to "core tiles" - Skylake-SP XCC die shot.

Each Sapphire Rapids "chiplet" would hold 15 "core tiles" and 1 "IMC tile" providing 2 DDR5 channels or so.

 

[scineram]

Ah, I thought memory controller would be on the sides.

We shall see I guess, but even if Intel will keep most of their market share, there is no way their margins won't take a hit.

They already kind of have.

 

[lobz]

Ah, I thought memory controller would be on the sides.

They already kind of have.

Nah, that's just the reintroducing of margin based innovation through avoiding the counter-progressive anti-degradation in even quarters, offsetting the negative effects of the current global market situation in the odd quarters, so the absolute value of their margins is actually always increasing, especially if you consider the rapidly expanding TAM - the TAM never lies, everybody knows that.

 

[ondma]

For once the thread is right where it should be, talking about ADL, AVX, SPR, and Intel execution in general. Why would you risk another derail just because you have an axe to grind?!

In response to Gideon's snide post.

 

[tomatosummit]

Ah, I thought memory controller would be on the sides.

The physical interface to the memory is on the sides but the controller is almost a separate part. I think intel's reasoning was that the controller being closer to the middle of the cores gives it a better average latency across all cores.

 

[DrMrLordX]

Of course nobody ever hypes AMD, right? Or turns Intel threads into AMD ones??

Two wrongs do not make a right.

IMO much more important than the exact performance of Sapphire Rapid itself, or even it's cost, is how much can Intel actually produce in 2022?

Based on the Mizuho report and the fact that 10nm production is still split between 10nm+ and 10SF/ESF, it's not hard to see that Intel would have no way of matching the volumes they got with Skylake-SP or Cascade Lake-SP.

Considering Ice-Lake SP still almost isn't available to anyone but hyperscalers has me a bit worried.

I think we're going to get a better idea on IceLake-SP availability in August or so when major OEMs start shipping rack systems made-to-order to smaller orgs. If you can log on to Dell at that time and configure a 2x40c IceLake-SP system that ships that day, then I would say Intel has good availability.

 

[IntelUser2000]

Sapphire Rapid die shots, looks like 15-16 cores per die to me:

Hmm, it was based on YuuKi_AnS shots that people thought SPR would go to 72 cores. But that image wasn't clear. Now we know the maximum is 56.

Is it me or the die area growing substantially with Golden Cove? The L3 cache size didn't seem to change, meaning the growth is all cores. It could 40-50% larger than Sunny Cove.

Alderlake without the 2x Gracemont cluster is going to approach 250mm2.

 

[Exist50]

Hmm, it was based on YuuKi_AnS shots that people thought SPR would go to 72 cores. But that image wasn't clear. Now we know the maximum is 56.

Is it me or the die area growing substantially with Golden Cove? The L3 cache size didn't seem to change, meaning the growth is all cores. It could 40-50% larger than Sunny Cove.

Alderlake without the 2x Gracemont cluster is going to approach 250mm2.

There's also AMX to consider. Must have a decent area penalty associated.

 

[lobz]

In response to Gideon's snide post.

You showed him..!!

 

[Saylick]

Hmm, it was based on YuuKi_AnS shots that people thought SPR would go to 72 cores. But that image wasn't clear. Now we know the maximum is 56.

Is it me or the die area growing substantially with Golden Cove? The L3 cache size didn't seem to change, meaning the growth is all cores. It could 40-50% larger than Sunny Cove.

Alderlake without the 2x Gracemont cluster is going to approach 250mm2.

You bring up a good point... It reminded me of the rumors that Gracemont performed roughly on par with Skylake, and I used to think that it was a remarkable achievement that they could fit four Gracemont cores within the same footprint as one Golden Cove core while still offering reasonable performance. I just realized that it's not that Gracemont is small for what it delivers, it's that Golden Cove is just silly large for what it brings to the table. It's simply not area efficient at all.

 

[IntelUser2000]

Just analyzed the die:

Sapphire Rapids, 2MB L2: 9.7mm2
Sunny Cove with 512KB L2 + 2MB L3: 6.91mm2
Sunny Cove without L2: 4.5mm2

I used to think that it was a remarkable achievement that they could fit four Gracemont cores within the same footprint as one Golden Cove core while still offering reasonable performance.

It's both being Tremont being incredibly area efficient and Core cores being incredibly inefficient.

See the figure of Sunny Cove without L2 being 4.5mm2? Well Tremont is actually only 0.85mm2. The ENTIRE Tremont cluster is only 4.9mm2. So that includes the 2MB L2 and the I/O that's required for a quad core cluster.

Core-only Tremont is only 0.85mm2. Sunny Cove is 5-6x as large, not 4x.

The Front End, the L3 cache, Load/Store units, or the Vector units are each a Tremont core!

 

[eek2121]

Re: die area

Each core tile in SPR should actually be 13-14mm^2 so 20mm^2 is a bit of a bad estimate. But die area matters a huge amount. To put things into context, here's a comparison of SPR vs Milan:

SPR: 4x~400mm^2 core tiles, all produced on Intel's 10ESF and packaged using EMIB. Total die area: ~1600mm^2

Milan: 8x~80mm^2 CCDs produced on N7, and 1 ~420mm^2 IOD produced on GloFo's 14nm. Total die area ~1060mm^2.

That's a very significant difference in die area, and a little under half of each Milan produced is even on a dirt cheap process node as well. Make no mistakes, there's a huge difference in production costs between the two. Even if you don't feel like area matters, you can be certain AMD and Intel both do - it directly affects their product margins. It also directly affects the number of maxed out chips they can actually sell too. It makes a huge difference when there's this much of a disparity.

Yes, it os a significant difference, but Intel still will make more money per chip than AMD because they own their own fabs.

Now more specifically in regards to this, but sorry, no SPR is almost certainly a power hog. 350W for similar or slightly better performance than the 20% lower power consumption Milan is not a great place to be in for a product that costs so much more to produce and almost certainly to buy as well.

PCIe5 and DDR5 are already very expensive, but we're also talking about ~1600mm^2 of 10nm put together with (albeit relatively cheap compared to other advanced packaging technologies) EMIB is not going to be cheap at all. SPR really needs a very solid win performance-wise over Milan to be worth it both for consumers and for Intel.

All these little bits and pieces add up when considering the value of a product. You already have more expensive technologies, but then you're also having to tack on additional power consumption costs as well?

On it's own, power consumption is far from a deal-breaker, so in that sense I agree with you. It's at least ok for the performance in question here. But it's just another thing that adds onto an already kinda long list of small issues that SPR has to deal with.

Don’t write off AVX-512. It is very important for certain workloads. That 350W TDP is likely with AVX workloads. Without it will likely be a bit lower.

The top Genoa chips are rumored to have a 370W TDP.

 

[IntelUser2000]

The Cortex A76 on Kirin 980 in TSMC's 7nm process is 1.2mm2 by the way. They need to do better in regards to power, but in terms of area Tremont is pretty damn good.

The top Genoa chips are rumored to have a 370W TDP.

Genoa is likely going to get AVX-512.

The only saving grace is maybe SPR will arrive a bit earlier, cause Genoa is going to make it worse than ICL-SP against Milan. Add to that V-cache boosting L3 cache is going to make it relevant for wider field of applications than HBM, and it has 12 memory channels as well.

 

[diediealldie]

When counting Zen 3 you need to factor in part of the IO die as well FYI.

There is nothing wrong with larger cores/dies. I personally don’t consider the chip to be a power hog for what it is. The top end SKU has a 350W TDP.

Sure we have to. But even if we assume that the Zen die size becomes two times bigger it's still 25% smaller than Golden Cove. Also need to note that AMD IOD's manufactured in inferior manufacturing node. Still smaller by a margin. As for a power consumption, who knows how Golden Cove is clocked.

I think it's related to chip design. Zen 3 did something smart so that they can improve IPC 10~15% with same frontend and backend, which Intel didn't. Intel simply followed square root law, and messed up by recent manufacturing conundrums.