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Discussion Intel current and future Lakes & Rapids thread

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dullard

Elite Member
May 21, 2001
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Which means that going for higher core counts with Golden Cove could be problematic, especially in their target market. But their competition is able to add up to 16c in consumer CPUs and get good perf/watt doing so. Intel needs to be able to do the same.
Isn't Intel going with large numbers of Golden Cove cores with Sapphire Rapids? I may be wrong, but weren't there rumors of 14, 28, 42, and 56 Golden Cove cores. That means HEDT chips could be made on the fully functioning 14 core version or a partially functioning 28 core version.
 

eek2121

Golden Member
Aug 2, 2005
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Isn't Intel going with large numbers of Golden Cove cores with Sapphire Rapids? I may be wrong, but weren't there rumors of 14, 28, 42, and 56 Golden Cove cores. That means HEDT chips could be made on the fully functioning 14 core version or a partially functioning 28 core version.
Intel could go with more “big” cores, but that makes the die bigger. If 4 “small” cores fit inside the space of 1 “big” core, and the “small” cores combined offer greater multithreaded performance, it is worth adding “small” cores instead.

EDIT: For fun I'm going to predict final GB5 scores for Alder Lake:

~2000 single core, ~17500 multicore.

Have fun! :)
 
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DrMrLordX

Lifer
Apr 27, 2000
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Isn't Intel going with large numbers of Golden Cove cores with Sapphire Rapids? I may be wrong, but weren't there rumors of 14, 28, 42, and 56 Golden Cove cores. That means HEDT chips could be made on the fully functioning 14 core version or a partially functioning 28 core version.
Sapphire Rapids may wind up being a major power hog. It's also going to be huge. LGA1700 has limits on how much power and area Intel can realistically commit to any CPUs hosted on that platform. It's possible that Golden Cove will make it hard for Intel to push for anything significantly higher than 8c on the consumer side (which was my point: Intel may be unable to do anything but stick extra Gracemont cores on Raptor Lake). As to whether Intel will launch an HEDT variant of Sapphire Rapids? They're welcome to try, and it would be interesting to see how that would turn out.
 

tomatosummit

Member
Mar 21, 2019
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Isn't Intel going with large numbers of Golden Cove cores with Sapphire Rapids? I may be wrong, but weren't there rumors of 14, 28, 42, and 56 Golden Cove cores. That means HEDT chips could be made on the fully functioning 14 core version or a partially functioning 28 core version.
I'd noticed a sapphire rapids tile looks disgustingly similar to a zepplin die at this point. A single tile on a mainstream desktop platform has the right amount of IO and a competative amount of cores. If some emib hbm fits on the package then there's a marketable alternative to 3dvcache.
 

DrMrLordX

Lifer
Apr 27, 2000
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I'd noticed a sapphire rapids tile looks disgustingly similar to a zepplin die at this point. A single tile on a mainstream desktop platform has the right amount of IO and a competative amount of cores. If some emib hbm fits on the package then there's a marketable alternative to 3dvcache.
Pretty sure a single-tile solution would still use mesh vs. ring though. It may also have different cache structure/associativity vs. client incarnations of Golden Cove (Alder Lake).
 

Ajay

Diamond Member
Jan 8, 2001
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The only solution I've been able to come up with for scheduling based on AVX-512 is to implement a scanner that parses all exe and associated dll files on a system for code unsupported on Gracemont. Then write {EXE_NAME, GC} to a data structure (hash table, b-tree) that is accessible in the scheduler, for all executables that don't have the require support on all cores. Each time a thread comes up for execution, it is tested against the data structure if if GC is returned, then execute on the big core, otherwise execute on the next available core. If there is a thread ID data structure, a new slot could be added to that data structure to speed this up a bit. There would have to be a bunch of other conditionals for backwards compatibility. Not pretty, but something like that might work and the it would push the heavy work to a pre-execution stage.

Other than that, I hate this design for desktop/enthusiast. A cut down version would probably be great for mobile. Like others have said, the only thing that makes sense is that this was a strongly marketing driven design choice. Meh.
 

jpiniero

Diamond Member
Oct 1, 2010
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Other than that, I hate this design for desktop/enthusiast. A cut down version would probably be great for mobile. Like others have said, the only thing that makes sense is that this was a strongly marketing driven design choice. Meh.
Don't forget that the Alder Lake-S die will also be used in mobile BGA. Granted it will be mostly aimed at gaming laptops and mobile workstations but they could still use the better idle.
 

lobz

Golden Member
Feb 10, 2017
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I've been around long enough to remember the first Intel chiplet processor. The internet reviews and forums turned Intel into a laughing stock calling Intel's chips "glued together". (see https://www.anandtech.com/show/1656/2 for one example) It is so odd for me to now see internet forums call for Intel to go back to chiplets (and of course people now think it was Intel that was making fun of AMD for gluing chips).

Your concept is very much what Intel is planning on doing:
You're confusing the reactions of press and some internet forum members with an official Intel PR slide here, God knows why.
 
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mikk

Diamond Member
May 15, 2012
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About 8+16 RPL from MLID.....Raichu hinted in March that RPL could be 24C and a month later he reaffirmed there is 8C16T+16C16T. 16+16 is hard to believe but assuming there is, I wonder if the rumored LGA18xx has something to do with it.
 

diediealldie

Junior Member
May 9, 2020
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Sapphire Rapids may wind up being a major power hog. It's also going to be huge. LGA1700 has limits on how much power and area Intel can realistically commit to any CPUs hosted on that platform. It's possible that Golden Cove will make it hard for Intel to push for anything significantly higher than 8c on the consumer side (which was my point: Intel may be unable to do anything but stick extra Gracemont cores on Raptor Lake). As to whether Intel will launch an HEDT variant of Sapphire Rapids? They're welcome to try, and it would be interesting to see how that would turn out.
Yeah, it'll be HUGE. That's what i'm worried about. According to leaks, the size of single SPR tile is almost 480mm2, with less than 20 cores per tile. Even if we assume that there are 20 cores per tile, the size of core will be 24mm2. Meanwhile, Zen 3 has a 80.7mm2 die size, with 8 cores per each(8mm2 per core). Probably only single tile HEDT's going to be released and decide not to fight against threadripper-class?

Anyway, even if we take IO stuffs and heavily stuffed AVX512 units into account, Golden Cove core is still too big. Golden Cove 'might' be 10~20% faster than Zen 3 in iso-clock comparison. Maybe Skylake descendants are too messed up?
 

lobz

Golden Member
Feb 10, 2017
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Well, I didn't believe in Comet Lake for Holiday 2019, let alone Q3 what was being pushed here at the time, and when it was """""launched""""" in Q2 2020, people were already talking about Rocket Lake being a Q3 or holiday-at-last 2020 product as a fact. When I (and a few other sober posters as well of course) pointed out how incredibly unprobable that was, some eager beavers went so far as to ridicule me, to much of my surprise.

By the same token I'm really reluctant to get excited when people are taking ADL and SPR as Q3 2021 products without even flinching, for some godforsaken reason. I'm also guessing, the reasoning against my comment will be the same for the 3rd time in a row: it's ready, it's been ready for quite some time, intel has to do it, intel _can_ do it etc. etc.

How many times can they play the same false game nkt only with investors but also with free thinking forumers too?
The only nice "surprise" from Intel in recent history was Coffee Lake and only because not much was known about it, especially about its timing - imagine that.
 
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tomatosummit

Member
Mar 21, 2019
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I'm suprised there's been no mention of a smaller die. Something to serve the ~24cores and under segments or would an icelake-x scc refresh be a better bet for that market?
 

eek2121

Golden Member
Aug 2, 2005
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Yeah, it'll be HUGE. That's what i'm worried about. According to leaks, the size of single SPR tile is almost 480mm2, with less than 20 cores per tile. Even if we assume that there are 20 cores per tile, the size of core will be 24mm2. Meanwhile, Zen 3 has a 80.7mm2 die size, with 8 cores per each(8mm2 per core). Probably only single tile HEDT's going to be released and decide not to fight against threadripper-class?

Anyway, even if we take IO stuffs and heavily stuffed AVX512 units into account, Golden Cove core is still too big. Golden Cove 'might' be 10~20% faster than Zen 3 in iso-clock comparison. Maybe Skylake descendants are too messed up?
When counting Zen 3 you need to factor in part of the IO die as well FYI.

There is nothing wrong with larger cores/dies. I personally don’t consider the chip to be a power hog for what it is. The top end SKU has a 350W TDP.
 

eek2121

Golden Member
Aug 2, 2005
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I'm suprised there's been no mention of a smaller die. Something to serve the ~24cores and under segments or would an icelake-x scc refresh be a better bet for that market?
If they are using tiles for this design, they can likely bin down as low as they want.
 

uzzi38

Golden Member
Oct 16, 2019
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Re: die area

Each core tile in SPR should actually be 13-14mm^2 so 20mm^2 is a bit of a bad estimate. But die area matters a huge amount. To put things into context, here's a comparison of SPR vs Milan:

SPR: 4x~400mm^2 core tiles, all produced on Intel's 10ESF and packaged using EMIB. Total die area: ~1600mm^2

Milan: 8x~80mm^2 CCDs produced on N7, and 1 ~420mm^2 IOD produced on GloFo's 14nm. Total die area ~1060mm^2.

That's a very significant difference in die area, and a little under half of each Milan produced is even on a dirt cheap process node as well. Make no mistakes, there's a huge difference in production costs between the two. Even if you don't feel like area matters, you can be certain AMD and Intel both do - it directly affects their product margins. It also directly affects the number of maxed out chips they can actually sell too. It makes a huge difference when there's this much of a disparity.
 

uzzi38

Golden Member
Oct 16, 2019
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I personally don’t consider the chip to be a power hog for what it is. The top end SKU has a 350W TDP.
Now more specifically in regards to this, but sorry, no SPR is almost certainly a power hog. 350W for similar or slightly better performance than the 20% lower power consumption Milan is not a great place to be in for a product that costs so much more to produce and almost certainly to buy as well.

PCIe5 and DDR5 are already very expensive, but we're also talking about ~1600mm^2 of 10nm put together with (albeit relatively cheap compared to other advanced packaging technologies) EMIB is not going to be cheap at all. SPR really needs a very solid win performance-wise over Milan to be worth it both for consumers and for Intel.

All these little bits and pieces add up when considering the value of a product. You already have more expensive technologies, but then you're also having to tack on additional power consumption costs as well?

On it's own, power consumption is far from a deal-breaker, so in that sense I agree with you. It's at least ok for the performance in question here. But it's just another thing that adds onto an already kinda long list of small issues that SPR has to deal with.
 

coercitiv

Diamond Member
Jan 24, 2014
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Personally I can't wait to see ADL-S pitted versus SPR-X, assuming Intel's HEDT line will get an upgrade within a reasonable time frame. I'll be very curious to see how the lowest HEDT SKU performs against ADL 8+8.
 

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