dullard
Elite Member
- May 21, 2001
- 25,921
- 4,510
- 126
[psst] You are supposed to get that the frequencies that are already low on Sunny Cove can be about 20% higher on Willow Cove.
We've already known that for a long time now. The reason they were brought into the thread now is that they were supposedly showing the V/F curve comparison between ICL and TGL (or more generically 10+ and 10SF). The whole discussion was that you can't rely on these charts for a V/F curve when the V is unlabeled and the charts aren't even consistent between themselves. I can't believe people are arguing that you don't need x-axis labels to get reliable and useful information, it's quite mind blowing honestly.
Edit: You are free to draw whatever conclusions you want though, I guess there's a reason marketing departments keep putting out graphics like this.
Lol, wasn't you the guy calling physical design considerations "technobabble", making extrapolation from unlabeled drawings from marketing and keep insisting that you can clock Gracemont to 4GHz no problem? And suddenly you figure out that there is a price to pay in terms of power and area when doing so? Love your moving goalposts, i really do!
Yet you completely failed to understand, that i was at least supporting your argument, that Gracemont can be clocked to 4GHz+ as can every ARM core, if you are willing to pay the price.
You cannot possibly test below Vth.
The tables you have linked are just sample values for process variations for a particular! device type, which designers might use for simulation/sign-off. The table could for instance show the process variations for an LVT device - but it is not even specified what device type the table is showing - or if it is related to any particular technology.
Last edited:
dullard
Elite Member
- May 21, 2001
- 25,921
- 4,510
- 126
Yes, which is why I said exactly what you said a few posts above. These are not for a specific CPU. These are frequencies that the microarchitecture could reach. In fact, Intel show various different graphs with different optimizations and different voltage curves. Vth for Intel's 10 nm logic gates is ~0.24 V.
Even every single CPU with the same model number will have a different curve. No two CPUs are identical. Some clock better than others. There is no one curve for all CPUs.
What you do get from the chart is that Willow Cove will have a higher frequency for each given voltage. That is useful information. People here can pretend it isn't true information all they want. Yes, it isn't the best graph ever made. But again, that is because it covers a whole range of different types of devices into one simplified graph. Willow Cove will clock higher than Sunny Cove, probably around 20% higher. If you disagree with that statement, please give us some data to use to agree with you.
Is there actual voltages in those Intel graphs? If there isn't, they might as well start from 0.5V or so where actual cpu designs start.
But as said above, those are pure marketing slides and have very little correlation to real world figures.....
But as said above, those are pure marketing slides and have very little correlation to real world figures.....
IntelUser2000
Elite Member
- Oct 14, 2003
- 8,686
- 3,787
- 136
Indeed it is a marketing slide. I think it has rough relevance to Tigerlake's gain over Icelake, since real world Tigerlake chips clock 15-20% higher. Icelake-SP also clocks terribly supporting their claims that it uses the same process as Jasper Lake and Icelake client.
How, is it an unknown when it matches silicon exactly? Are you going to try telling me it it does a loopy-loop in the middle or something?
I have. At both a high efficiency point (~TDP) and Vmax (max frequency), we see the same things the graph shows. So why is it so difficult to believe? It's absurd that there's still denial about the benefits of 10++ when we have concrete proof.
Mate, you're attributing a quote to me. Might want to reread some comments. And yes, it's technobabble to refer to design considerations when that's already been adjusted for in the comparison. Or are you going to try telling me that Willow Cove has a radically different design from Sunny Cove? It's nonsense, an attempt to fabricate an excuse from thin air.
Last edited:
If you have hard data to share, please do, it would be interesting to see.
How did you adjust for anything? By simply claiming an apples to apples comparison? Heck, you don’t even know what has been fixed at all, whether it was a specific process deficiency, or if the design was tweaked to take advantage of a process change, you don’t know anything at all. Then you furthermore apply your know-nothing nonsense to a different architecture, different design, different power target, different frequency target, and try to claim some generic linear increase. Utter garbage.
You were dead wrong on Rocketlake and tried to lie your way out and now you are blabbering on about Atom at 4ghz. Better screencap this so you don’t try to lie your way out of this one too.
Look at the TGL SKU list compared to ICL. Compare at TDL and max boost clock.
If you were paying any attention, you'd know that Willow Cove is basically the same core as Sunny Cove.
Lmao, sure, let's forget literally every known fact about process improvements. And as pointed out, we're talking about effectively the same architecture, design, and power targets.
And this is extra funny when you didn't know that Tremont was on 10+ in the first place.
On the contrary, you claimed it would do none of the things that it did (clocks, IPC, power). Can't say the same for me. Go ahead, screenshot this. I'm sure you'll conveniently forget later, and move on to trolling about some other topic.
Oh yeah? And what are those process improvements? Effectively the same how? Do you even know how many years Intel spent tweaking on the Tigerlake core?
What makes you say that? I said Atom won’t be run at 4ghz. I didn’t even bother naming a 10nm process version, because it would be superfluous and unnecessary. To be clear: it won’t run that fast *regardless* of what 10nm process it is on. That high of a clock is contrary to the design goals of the architecture, it is contradictory to the die size and power per perf goals of that core. These are real engineering concerns that you are just utterly clueless about.
LOL, say what now? I didn’t say RKL would:
Suck down a crazy amount of power
Have worse power efficiency than its predecessor on iso performance
Not reach the insane clocks being tossed around here
Oh do tell, what did I say instead of those things?
Again, this has all be basic knowledge for anyone who's been paying any attention.
Ah, so it's just pure ignorance. Both ARM cores and Atom have been increasing in clock speed with the generations. Tremont achieves 3.3GHz, significantly higher than any Atom core before it, despite being on a node that we know is ~20% slower vs the latest. So, unless you claim Gracemont is, for some reason, going to reverse the historical trend, then it should be able to hit around 4GHz.
Oh do tell, what did I say instead of those things?
Can't backport with decent clock speeds (or backport at all), can't have lower TDP SKUs, etc. Every time you tried to make a specific claim, you were wrong.
Meanwhile, do go ahead and post my claims. I've certainly not deleted anything, so feel free to browse.
Again, this has all be basic knowledge for anyone who's been paying any attention.
Ah I see, you consider marketing slides to be canonical. It all makes sense now.
Pro-tip: it is because they increased the power limit during turbo, not because of some "historical trend". As for your 20% slower generic claim, that is total nonsense and the actual early 10nm deficiencies are so far beyond your capabilities I will not bother to even try to explain.
Nice try. I said the Rocketlake backport is unprecedented in Intel's history because it is a technological regression. I never said anything about not being able to backport at all, since that would be stupid and only you can imagine that up in your feverish delusions. As for clocks, go look at the base clocks and power consumption... pretty much says it all.
Anyways, enough of this... spent the whole week designing silicon that doesn't suck so now I have a couple days to rest.
If you have proof they're lying, post it. Otherwise you're clearly unwilling to accept reality.
Not true for ARM, and not true for Atom. It's amazing how shameless you BS.
Sure you are... The guy who think process scaling is a lie totally works in the industry.
Ya sure... where's your EE degree?
Not willing to fish it out of storage just to post on the internet, thank you very much. Not that you need a degree to make any of the observations I've pointed out.
IntelUser2000
Elite Member
- Oct 14, 2003
- 8,686
- 3,787
- 136
Tigerlake does clock much higher, and both Icelake chips clock terribly and can't go over 4GHz. Well, I guess one super binned part that went to Apple, only achieved by setting the TDP at 28W. The Xeon does much worse with max frequencies at mere 3.7GHz.
Getting a 20% gain due to a process change is a near generational improvement. If that doesn't tell you how crap 10+ was, nothing will. A much more subtle and iterative improvement is observed with endless plusses on their 14nm, when top clocks increased by 100-200MHz.
And you are suggesting Intel somehow had many more years tweaking Tigerlake than Icelake, when the former came out year later than the latter.
Yeah, you must not have a degree to say things that dumb. Or maybe your school owes you a refund.
Top clocks are a gimmick. The issue was always variation. It takes a dozen transistors out of millions on a path to be slow to wreck your frequency. That also takes out your top clocks because those mismodeled paths often to do not respond to voltage increases.
Yeah. They had all the time in the world to tweak their databases while 10nm was unusable. Even back in 2016 when I was still wasting my time at Intel, Tigerlake was already months old.
Do you have any clue when they started working on Icelake? Seriously, just stop for your own sake.
Yes, actually. Ice Lake came before Tiger Lake, and Tiger Lake did not exist in 2016. That's the last of this nonsense I'm going to entertain.
But it did. Google search? https://www.hardwarezone.com.sg/tech-news-rumor-intels-third-10nm-cpu-may-be-known-tigerlake Rumors as early as Jan 2016. Just because 10 nm was broken does not mean the designs had not begun.
DrMrLordX
Lifer
- Apr 27, 2000
- 22,720
- 12,695
- 136
mmmm actually you may want to walk that back a bit.
Intel's 10nm 'Cannonlake' delayed, replaced by 14nm 'Kaby Lake'
Intel has led the desktop processor market for the last decade, dominating in price and performance nearly without challenge since the introduction of the Core 2 chips...
www.techspot.com
How soon we forget. Cannonlake was supposed to be in retail silicon in 2016. In quantity. Kaby wasn't even supposed to exist. If Cannonlake was ready on a design level for a 2016 launch, where do you think IceLake and TigerLake were . . . ?
(oh, and top of that, Skylake and Broadwell were also delayed)
TRENDING THREADS
-
Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)- Started by DisEnchantment
- Replies: 25K
-
Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads
- Started by Tigerick
- Replies: 21K
-
Discussion Intel current and future Lakes & Rapids thread- Started by TheF34RChannel
- Replies: 23K
-
-
Facebook
Twitter