Discussion Intel current and future Lakes & Rapids thread

[dullard]

IIRC it started on June 8 with the "Tiger's Roar" promo material sent to the press and June 17 with the BF5 gameplay demo from Ryan Shrout.

To continue the timeline:

• Official press release Sept 2. I assume this is the date the chips were sent from Intel to manufacturers and thus information could no longer be controlled: https://www.anandtech.com/show/1606...n-core-tiger-lake-processors-and-evo-branding
• The laptops started to be available for order from major manufacturers Oct 1 (delivery late Oct): https://www.dell.com/en-us/member/s...spd/xps-13-9310-laptop#configurations_section
• Intel's Fab 42 to produce Tiger Lake chips operational on Oct 6: https://www.tomshardware.com/news/intels-long-awaited-fab-42-is-fully-operational

 

[ondma]

It sounds like your timeline is on the order of a year. Intel's timeline is on the order of a decade.

Huh?? Care to explain?? If you are hemorrhaging market share in desktop, server, and mobile, seems like you would want to remedy that before worrying about 10 year timelines. Tiger Lake may be a good start in mobile, but they dont seem to be catching up in desktop or server. (Probably due still to lousy 10 nm yields making higher core counts a problem.)

 

[arandomguy]

Huh?? Care to explain?? If you are hemorrhaging market share in desktop, server, and mobile, seems like you would want to remedy that before worrying about 10 year timelines. Tiger Lake may be a good start in mobile, but they dont seem to be catching up in desktop or server. (Probably due still to lousy 10 nm yields making higher core counts a problem.)

Those overall marketshare (and product) issues aren't related to or solveable by a >8 big core product (Alder Lake) for the desktop DIY market. DIY is not the most pressing market for Intel nor AMD much less the even smaller sub group looking for >8 big cores at this point in time. Neither develops for DIY (essentially us) as their core focus.

AMD will win the "core" battle for DIY for the foreseeable future as it trickles down server to that segment. Intel has historically (and looks to still be) "trickled up" mobile (and OEM desktop) so to speak.

 

[IntelUser2000]

Am I the only one interested in the L2 cache configuration?

10x 1.25MB L2

Seems that a Small Core cluster gets 1.25 MB L2 and the whole chip has 30 MB L3.

edit: if there is no L3 for Gracemont it would result in 3.75 MB L3 per core for Golden Cove. We don't know if Gracemont gets a separate L3.

My guesses.

8x 1.25MB L2 for 8 Golden Cove cores
2x 1.25MB L2 for dual quad core clusters in Gracemont

8x3MB L3 for 8 Golden Cove cores, which means it stays identical to Willow Cove
2x3MB L3 for dual quad core Gracemont clusters

 

[JoeRambo]

Am I the only one interested in the L2 cache configuration?

10x 1.25MB L2

Cache hierarchy usually comes from CPUID instruction leafs, so program doing identification needs to be aware about exact encodings of said leafs. Unfortunately not Sisoft.

For example Lakefield monstrocity

Details for Result ID Intel(R) Core(TM) i5-L16G7 CPU @ 1.40GHz (5C 1.38GHz/3GHz, 2x 1.5MB L2, 4MB L3)

ranker.sisoftware.co.uk

is reported as
Details for Result ID Intel(R) Core(TM) i5-L16G7 CPU @ 1.40GHz (5C 1.38GHz/3GHz, 2x 1.5MB L2, 4MB L3)

When we know it has the following cpuid:

https://github.com/InstLatx64/InstLatx64/commit/382580dc9f5fbed23cb1945c6b4a259a49cab484

So reporting could be completely off for those bastard sons of Intel marketing.

 

[Cardyak]

My guesses.

8x 1.25MB L2 for 8 Golden Cove cores
2x 1.25MB L2 for dual quad core clusters in Gracemont

8x3MB L3 for 8 Golden Cove cores, which means it stays identical to Willow Cove
2x3MB L3 for dual quad core Gracemont clusters

Yes, this makes the most sense.

So in effect:

	Golden Cove	Gracemont
L2 per Core	1.25MB	~0.31MB
L3 per Core	3MB	~0.75MB

 

[JoeRambo]

No reason for Intel to degrade small core cluster to 1.25MB instead of 1.5MB Lakefield had. Like i posted above, Sisoft is simply taking CPUID and walking cache leafs without properly understanding it for these heterogenous CPUs.

It was reporting 512 + 1.5MB L2 as 2x 1.5MB L2, basically ignoring large core config.

If I were to make educated guesses, then L2 1.25MB is for Golden Cove and it is enumerated first, and then there are two clusters of small cores, with cache size that is currently unknown without full printout of CPUID instruction.

 

[dullard]

Huh?? Care to explain?? If you are hemorrhaging market share in desktop, server, and mobile, seems like you would want to remedy that before worrying about 10 year timelines. Tiger Lake may be a good start in mobile, but they dont seem to be catching up in desktop or server. (Probably due still to lousy 10 nm yields making higher core counts a problem.)

The start of this discussion was about hybrid chips. Thus, my comment was about hybrid chips. Intel has a long term plan that they have outlined to have different hybrid chips for different market segments. This will not happen overnight, nor will it happen this year. Businesses need a long term vision, and this is Intel's long term vision. They are starting it on mobile, but don't expect it to stay just mobile. When it hits desktop, some chips will not be for you and will look terrible for your use cases. This is because Intel is going to differentiate CPUs for different markets in new ways that we have not yet experienced.

Intel doesn't have a market share problem. Intel is selling every single chip it can possibly make, immediately, and at high prices. That is actually quite good for a business if you think about it. Instead, Intel has a production problem. You are correct that this long-term hybrid chip plan will not address Intel's immediate production problem. But it doesn't have to address it directly either.

To answer your "Why not just make 16 (or 12 or whatever) big cores" question, it is because Intel can't make it with their current production limitations. To get out as many chips as possible to meet the very high chip demand, Intel cannot focus on big, lower yield chips. But, Intel can make a chip that is just as good in many (but not all) use cases with 8 big cores and a few little cores.

 

[naukkis]

No reason for Intel to degrade small core cluster to 1.25MB instead of 1.5MB Lakefield had.

Actually as L3 has L2 shadow tags keeping L2-caches identical every L3 Slice would be equal. Increasing one slice L2 could result slower performance L3 for whole system.

 

[uzzi38]

Hey guys, maybe an odd question, but when did Intel start all the Tiger Lake teasing bs several months ago now? I forgot the actual first date they starting doing that stuff

So remember when I asked this yesterday?

...well yeah, there was a reason.

AnandTech Forums: Technology, Hardware, Software, and Deals

Seeking answers? Join the AnandTech community: where nearly half-a-million members share solutions and discuss the latest tech.

www.anandtech.com

 

[inf64]

So remember when I asked this yesterday?

...well yeah, there was a reason.

AnandTech Forums: Technology, Hardware, Software, and Deals

Seeking answers? Join the AnandTech community: where nearly half-a-million members share solutions and discuss the latest tech.

www.anandtech.com

If they intend to sell that thing for a year, where does that put Alder Lake for desktop?

 

[uzzi38]

If they intend to sell that thing for a year, where does that put Alder Lake for desktop?

I don't think they do.

I still personally stick by the rumours stating ADL-S will launch in 2021 and it'll be the first ADL die to launch too. I just think Rocket Lake might as well be canned at this point. It's so unbelievably late and probably won't even perform well enough to be worth that wait over waiting a little more for Alder Lake. Or just nabbing Zen 3.

 

[coercitiv]

I still personally stick by the rumours stating ADL-S will launch in 2022 and it'll be the first ADL die to launch too. I just think Rocket Lake might as well be canned at this point. It's so unbelievably late and probably won't even perform well enough to be worth that wait over waiting a little more for Alder Lake. Or just nabbing Zen 3.

I'm a bit confused: you consider waiting 1 year for ADL-S as "a little more"?

 

[uzzi38]

I'm a bit confused: you consider waiting 1 year for ADL-S as "a little more"?

...typo

Meant 2021.

Goddamn it me.

 

[dullard]

So remember when I asked this yesterday?

...well yeah, there was a reason.

AnandTech Forums: Technology, Hardware, Software, and Deals

Seeking answers? Join the AnandTech community: where nearly half-a-million members share solutions and discuss the latest tech.

www.anandtech.com

I don't quite understand your point.

With desktops processors, the moment you have the chip, you have something you can sell. With mobile processors, you have to do extensive design work to deal with the intricacies of heat transfer on a CPU with variable power usage in limited space. So, what does the time between a mobile processor's announcement and retail availability have to do with your desktop chip link?

 

[uzzi38]

I don't quite understand your point.

With desktops processors, the moment you have the chip, you have something you can sell. With mobile processors, you have to do extensive design work to deal with the intricacies of heat transfer on a CPU with variable power usage in limited space. So, what does the time between a mobile processor's announcement and retail availability have to do with your desktop chip link?

Because you're looking at a teaser nearly 6 months before you get availability.

 

[JoeRambo]

Actually as L3 has L2 shadow tags keeping L2-caches identical every L3 Slice would be equal. Increasing one slice L2 could result slower performance L3 for whole system.

That assumes that small core clusters have L3 slice at all. What if there are just 8 L3 slices next to big cores instead? It can work both ways.

Also would not rush into assumptions about tags, 1.25MB of L2 is large to keep shadow tags for, might as well use actual cache tags. It is now "decoupled" by not being inclusive, might give them opportunities to do just so. ( <- not an expert here )

L2 Cache size is very important for small core cluster performance. At 1.5MB size it is already smallish, since it is shared by all 4C. Good for Cinebench, but not much else.

 

[IntelUser2000]

Yes, this makes the most sense.

So in effect:

	Golden Cove	Gracemont
L2 per Core	1.25MB	~0.31MB
L3 per Core	3MB	~0.75MB

Unlike on Core, L2 caches are not private and is similar to how it was in the Core 2 days.

Also in this case, Sisoft could very well be accurate because it says its 10x L2 caches.

I just think Rocket Lake might as well be canned at this point. It's so unbelievably late and probably won't even perform well enough to be worth that wait over waiting a little more for Alder Lake. Or just nabbing Zen 3.

Rocketlake can have a slightly shorter lifecycle for one reason: It's the CPU upgrade for the 400 series chipset that Cometlake works on. Unlike Alderlake with many more pins, new DDR standard, yet even newer PCI Express standard.

Also it was announced as having future support for PCIe 4.0 on many motherboards.

Motherboards have RGB strips on them purely for the sake of standing out, do you really think PCIe 4.0 is a trivial point for them? Or that it supports 11th Gen?

I don't think Alderlake-S will arrive anytime before late-November if it does arrive this year. That's a significant profit loss both for component manufacturers and Intel, since beyond 12 month sales volume start to drop.

 

[dullard]

Because you're looking at a teaser nearly 6 months before you get availability.

Yes, but do you have a point? CPUs details are leaked, benchmarks can be spotted, announcements are made, all well before the CPUs are available. That is all true. But what do you want to tell us about it?

We've been hearing about Rocket Lake and Zen 3 for ages. Little drips here and there. Is your point that you wish for this to stop?

 

[uzzi38]

Yes, but do you have a point? CPUs details are leaked, benchmarks can be spotted, announcements are made, all well before the CPUs are available. That is all true. But what do you want to tell us about it?

We've been hearing about Rocket Lake and Zen 3 for ages. Little drips here and there. Is your point that you wish for this to stop?

We can continue this discussion in a week or so.

 

[dullard]

We can continue this discussion in a week or so.

So, your point is that Zen 3 being available means that no one would want Rocket Lake? Just come out and say it or don't say anything.

 

[uzzi38]

So, your point is that Zen 3 being available means that no one would want Rocket Lake? Just come out and say it or don't say anything.

My point is that teasing and generating hype for products 6 months ahead of when they will actually launch us a trend that should die. And I said wait a week or two so you can see that in action

I'm not sure how you figured out your own interpretation. I never said Zen 3 being available means nobody should get Rocket Lake. I said the combination of Alder Lake-S being available by the end of 2021 AND Zen 3 becoming available soon means that interest in Rocket Lake should be low.

Alder Lake will be a step up for 1T perf on a much not-dead platform. Zen 3 will crush Rocket Lake in MT perf and will be extremely close in 1T perf.

What's with all the seethe at the mention of Zen 3?

 

[dullard]

My point is that teasing and generating hype for products 6 months ahead of when they will actually launch us a trend that should die. And I said wait a week or two so you can see that in action

Thank you for actually saying what you want us to know. Leaks and hype are just a part of the business.

Intel had Rocket lake leaks about 2 years before launch: https://www.tomshardware.com/news/intel-roadmap-10nm-14nm-gpu-cpu,39163.html
Intel started hyping Rocket Lake maybe 6 months before launch (time will tell exactly how long).

AMD started hyping Zen 3 a year before launch.

AMD Dishes on Zen 3 and Zen 4 Architecture, Milan and Genoa Roadmap

A now-removed presentation from an HPC conference shines the light on AMD's roadmap and change to its next-gen processors.

www.tomshardware.com

I'm sure someone here can dig up even earlier references than my quick Google search turned up.

 

[uzzi38]

Thank you for actually saying what you want us to know. Leaks and hype are just a part of the business.

Intel had Rocket lake leaks about 2 years before launch: https://www.tomshardware.com/news/intel-roadmap-10nm-14nm-gpu-cpu,39163.html
Intel started hyping Rocket Lake maybe 6 months before launch (time will tell exactly how long).

AMD started hyping Zen 3 a year before launch.

AMD Dishes on Zen 3 and Zen 4 Architecture, Milan and Genoa Roadmap

A now-removed presentation from an HPC conference shines the light on AMD's roadmap and change to its next-gen processors.

www.tomshardware.com

I'm sure someone here can dig up even earlier references than my quick Google search turned up.

Since when were leaks official teasers/announcements?

Both of those are leaks.

 

[piokos]

Since when were leaks official teasers/announcements?

Both of those are leaks.

How exactly is "presentation from an HPC conference" a leak?

Seriously, AMD has been called out on hyping (even very distant) products for many years. I don't understand your motivations, but neglecting that just makes you look silly. Don't go that path.

Just remind yourself how the year before Zen looked. And with Zen2 launch AMD said they have 2 leapfrogging design teams - basically saying that they'll be hyping 2 future generations instead of one.
And what about RDNA2? How long has that been going on? 😀

As @dullard said: hyping products is part of this business. And AMD has been doing this more simply because they were building the image of an enthusiast brand.
In reality neither of these brands really focuses on the DIY enthusiast niche. It's just that Intel doesn't even give a f... to fake it (something I appreciate, to be honest).