I don't buy this, not for performance in consumer desktops. The ratio between small and big cores doesn't bring that much of an advantage if you take into consideration the higher thread count needed to reach optimal throughput, not to mention the fact that it likely requires tasks with low MT diminishing returns to get there.
8 big + 8 small (1x area)
8 x 1.5 x 1.2 = 14.4
8 x 1 = 8
Throughput @ 24T = 22.4
Throughput @ 16T = 20
Throughput @ 12T = 16
Will require dual ring bus, some kind of mesh or new type of interconnect.
Latency sensitive tasks will probably run only on the big cluster for best results.
10 big (1x area)
10 x 1.5 x 1.2 = 18
Throughput @ 24T ~ 18
Throughput @ 16T = 16.8
Throughput @ 12T = 15.6
Same old ring bus, all cores readily available for everything.
12 big (1.2X area)
12 x 1.5 x 1.2 = 21.6
Throughput @ 24T = 21.6
Throughput @ 16T = 19.2
Throughput @ 12T = 18
Maybe too much of a stretch for ring bus, maybe still doable.
8 big + 16 small (1.2X area)
Throughput @ 32T = 30.4
Throughput @ 24T = 28
Throughput @ 16T = 20
Throughput @ 12T = 16No. I also think Intel is not going to rush to follow AMD and put 16 strong cores on client desktop. They'll prefer to counter a potential 16 core AMD future chip with a low priced HEDT chip. Only heaven knows why AMD chose to cut of their HEDT lineup at the 24 core mark.
Their HEDT lineup goes to 64 cores, threadripper is HEDT.
Interesting, that explains a lot.
Yes, but the first generation TR bottomed out with the 1900x 8 core. Second generation bottomed out with TR 2920x 12 core. Following that logic, the Third generation TR should've at least bottomed out with the 16 core 3950x.
I'm pretty sure AT had theirs run at 3.9GHz.
