Dayman1225
Golden Member
- Aug 14, 2017
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With 26c Max I’m not quite sure how this works but...
It said 14 nm. They already have a 28 core 14 nm, so I don't see the big deal.not that bad that they can do 26C with their 10nm
sounds promising
I still think they have some big bomb incoming in late 2019/early 2020
With 26c Max I’m not quite sure how this works but...
He’s referring to the 26c Icelake listed there. 10nmIt said 14 nm. They already have a 28 core 14 nm, so I don't see the big deal.
Hmm, well if Cooper on Whitley is going to be 350+ W TDP, I suppose they could offer similarly high TDP models for Icelake even though it has half the cores, with a juiced up AVX-512 clock as the main beneficiary.
I thought we were talking about fmax potential and frequency ceiling of 10n / 7nm, not whether the architecture needs improvement or not.
ajc9988 said:But Intel is using density for marketing and misleading on being most dense in regards to their chips because of a theoretical SRAM density.
DrMrLordX said:26 core IceLake? Are they going to make an AP die out of that with . . . 52 cores? 48 cores?
So it appears this roadmap does not show everything
Ah, I see what you were referring to now. There's a very important difference between SNB and CFL there too. The former had great OC headroom. The latter achieves "high clocks" by simply eating up headroom. Unchanging uarch/process would have meant insane amount of time to characterize the silicon to maximize out of box frequency.
When Intel said they were abandoning Netburst because clock and voltage scaling was dead, its true today as it was then.
Yes they can. And I don't think its SRAM they are referring to, because 14nm SRAM didn't get the claimed density benefits over 22nm SRAM cells, and it was the historical 45-50% reduction. But I know one chip that did.
Atom. The 14nm Airmont core got an amazing 64% reduction in size compared to the 22nm Silvermont one. That's 2.78x the density, just like it was claimed: chrome-extension://oemmndcbldboiebfnladdacbdfmadadm/https://newsroom.intel.com/newsroom/wp-content/uploads/sites/11/2017/09/mark-bohr-on-intels-technology-leadership.pdf
The Goldmont core, even with substantial advancement over Airmont, is still small enough that you can fit 6-7 of them in the size of one Skylake-class core. Or putting it another way, you could fit nearly 4 Goldmont cores, its L2 caches, and the System Agent equivalent in 1 Skylake core without the L3 cache.
The density focus in a way did pay off in some aspects. It's just that its less than expected because phones went nowhere.
They don't have to. This is what I meant by preventing cannibalization. By keeping Icelake at 26 cores, you still give a reason for vendors to buy Cooper Lake. Rather than allowing Broadwell-C to be at high clocks, have the GT3e GPU and eDRAM, they kept the TDP low and clocks low so Skylake desktop would have its place.
well I am not convinced that everyone wants moar coarz....
there are lots of software with license based on core count
if Intel can deliver per core/thread count much higher performance it has a big selling potential
ofc pure cloud VMs and epyc 64C are in love, there intel doesn't reach, only if they offer something with EMIB/foveros/whatever....or the glue
They don't have to. This is what I meant by preventing cannibalization. By keeping Icelake at 26 cores, you still give a reason for vendors to buy Cooper Lake. Rather than allowing Broadwell-C to be at high clocks, have the GT3e GPU and eDRAM, they kept the TDP low and clocks low so Skylake desktop would have its place.
Is 26c IceLake going to be as scarce as Broadwell-C? That chip was mostly non-existent. It shipped in volumes far below that of Skylake. Broadwell-C wasn't going to cannibalize anything.
I would not focus on full 26C die being enabled and sold.
Part of that is capacity, the other part competition. For the capacity part, due to yields and due to the number of fabs capable of producing 10nm designs, you can only produce certain lines, not all lines for all markets. Further, Intel has planned for years to switch to server being served first before mainstream. And due to limited capacity, you would target the highest margin parts. Hence, Xeons. As to competition, Intel has been the main chip provider for x86 based tablets, netbooks, and notebooks. Due to their 14nm capacity issues, it hit laptop manufacturers hard, causing them to expand AMD offerings. So Intel feels pressured to address that threat first.Okay, I guess I should rephrase my question to include any of the mid-to-high density IceLake server SKUs. I'm still flabbergasted that IceLake server can exist at all when Intel has no IceLake desktop parts in 2020 and only 4c mobile parts in quantities that are allegedly going to be pretty limited.
And due to limited capacity, you would target the highest margin parts. Hence, Xeons.
Margins are better, as a wafer costs $11000 and their current 28-core chips fetch $10,800. If you limit the line so that you make it back on a single good chip, and a couple partially disabled, you would be OK. Not great on margin, but better than selling each desktop chip at $500-1000 while competing with Zen 2.Are the margins really better if you only get like 5 sellable chips per wafer, and that includes partially disabled? That's why I've been saying it's more for Shareholder PR than anything else.
Part of that is capacity, the other part competition.
Second, comparing the density of two products does NOT look at the density achieved relative to the stated density on a process node. By that, I mean relative density between generations does not speak to node density or being able to achieve the published densities on a node, thereby making the comparison superfluous to the discussion of actually achieving claimed densities.
DrMrLordX said:I'm still flabbergasted that IceLake server can exist at all when Intel has no IceLake desktop parts in 2020 and only 4c mobile parts in quantities that are allegedly going to be pretty limited.
I would not focus on full 26C die being enabled and sold.
Nonsense. You don't put "26 core die but you can use only 22 cores" on a roadmap. If that's a relevant roadmap, then we'll see a 26 core SKU. They don't have to ship a lot of them.
I meant exactly the same, being non native English speaker is hard to find exact words.
Clearly, they still have issues, but maybe not as catastrophic as some make it out to be. It went from being a disaster to just being bad?
2 working dice per wafer would still be catastrophic. 26 cores per die on 10 nm is going to be, what, ~150 DPW - ballpark? Even a miserable yield of 15% would only garner ~20 dice per wafer - just terrible.I guess if they are getting one or two working dice per wafer then that would explain it.
2 working dice per wafer would still be catastrophic. 26 cores per die on 10 nm is going to be, what, ~150 DPW - ballpark? Even a miserable yield of 15% would only garner ~20 dice per wafer - just terrible.
I was just spitballing (we don’t know any 10nm yield data). If Intel is actually getting something like 15% yields on Y/U processors, then Icelake-SP is just another dog and pony show. 1 or 2 dice per wafer is catastrophic.I'm not sure how the industry measures yield rate when the node is being used on different die sizes. If you have 15% yield on 2c dice, unless all the "good" dice come from the same region of the wafer on every wafer, there's no way you get 15% actual yields when you try 26c dice on the same wafer using the same process. Someone else (sorry, I forget who) on these forums ran the math, and the wafer costs are low enough that one 26c die per wafer would at least pay for the wafer (if not R&D, packaging, shipping, etc). Two dice would actually turn a tiny profit. It would be enough to at least bamboozle investors into believing that 10nm is "just fine".