Discussion Intel current and future Lakes & Rapids thread

[itsmydamnation]

No question that it's more MT throughput than needed. Sure rendering, transcoding, and some other tasks will always be able to make use of more cores. But that's getting beyond the 'mainstream' realm which likely wouldn't notice any difference between a 4P+8E configuration and 8P.

Another way to put it. Intel learned their lesson with respect to core counts - it's better to have the 'benchmark wanking' product rather than let the competition run with it.

even one you listed transcoding will prefer a smaller number ( ~8-16) of high performance cores then a sea of lower performance cores ( 16+ )

 

[Thunder 57]

https://twitter.com/i/web/status/1703842115875217736

Pat is ready 😁🏅💻

I'm sure you are too.

 

[SiliconFly]

I think that is where we differ. When there are plentiful E cores, there would be no need to preempt the preferred cores. We could finally have dedicated cores to our important programs with no* context switching, no preemption, etc. of those important tasks.


* Yes, gdansk, there would still be context switching of the unimportant tasks on unimportant cores.


"Usually" is not sufficient in my experience. I see all kinds of stutters and delays when background tasks kick in. Maybe it is fine with your tasks. But certainly not for me.

Well, as of now there is no way to avoid context-switching completely. But we can mitigate the effects of context switching by setting process affinity & core pinning.

 

[JoeRambo]

But we can mitigate the effects of context switching by setting process affinity & core pinning.

Only partially. Even on same core if process A ran, then process B ran, once process A needs to run again, it will find TLBs, branch predictors etc etc flushed. Even with caches it's not straitforward due to ASID usage and the common sense fact that B "ran" and evicted lines of A's first run.
It will take a lot of cycles for process A to reach peak perf due to TLBs and BPs needing refilling and 'training".

 

[FangBLade]

https://twitter.com/i/web/status/1703842115875217736

Pat is ready 😁🏅💻

Ah, I remember the time when Intel was a serious brand.

 

[eek2121]

https://twitter.com/i/web/status/1703842115875217736

Pat is ready 😁🏅💻

I’ll catch the rerun and read the spoilers online.

 

[Geddagod]

Ah, I remember the time when Intel was a serious brand.

Don't know why you hating, I love goofy ahh Intel lol

 

[S'renne]

Don't know why you hating, I love goofy ahh Intel lol

same and also different generation different type of customers lol it's gonna be the funniest thing ever to some people

 

[FangBLade]

Don't know why you hating, I love goofy ahh Intel lol

I don't hate them, but I facepalm. Intel has fallen quite low, and these foolish things they do with push-ups to raise people's interest confirm their status.

 

[Geddagod]

288 core SRF revealed, Intel sandbagging is a bit refreshing.

 

[jpiniero]

288 core SRF revealed, Intel sandbagging is a bit refreshing.

Sounds toasty.

 

[lightisgood]

Pat displays 288C SRF, yes, this is cleary SRF-SP.
I wish 432C SRF-AP will come...

 

[adroc_thurston]

Pat displays 288C SRF, yes, this is cleary SRF-SP.

That's -AP, it uses 7529 package.

Intel sandbagging is a bit refreshing.

As sandbagging as CL-AP or CPX-4 kek.

 

[lightisgood]

That's -AP, it uses 7529 package.

Yes, I made a mistake.

Intel Announces 288 E-Core Sierra Forest Variant at Innovation 2023

At Intel Innovation 2023 Intel formally disclosed that it will have a 288 core Sierra Forest Xeon with all E-cores for cloud-native servers

www.servethehome.com

 

[Henry swagger]

Mild was right on all his intel leaks lol

 

[Geddagod]

Mild was right on all his intel leaks lol

esp on his 20% RWC IPC leak lol

 

[Geddagod]

Genuinely think Intel borked their slides accidentally, or Intel pulled up like waaaay faster than anyone thought they could. PTL before 2025 sounds wild.

 

[jpiniero]

That's -AP, it uses 7529 package.


As sandbagging as CL-AP or CPX-4 kek.

Oh if it's AP, it's basically vaporware.

 

[Henry swagger]

Arrow lake is 20A confirmed 😄✅ .. lunar lake is looking good

 

[adroc_thurston]

Oh if it's AP, it's basically vaporware.

No, but it's a stillborn product and given that SRF-AP wasn't on the roadmaps...
Platform readiness lol

 

[Dayman1225]

I said pretty recently 144c was max, I was wrong. Intel kept that secret pretty well. It was removed of roadmaps months ago. Now it’s back. Is this what it feels like to be MLID? 😂

 

[JoeRambo]

Arrow lake is 20A confirmed 😄✅ .. lunar lake is looking good

I am starting to think, that ARL performance estimates were like being Sierra Forrest 144C only -> designed to weed out rabid leakers.
If it is really on 20A, numbers we were "given" don't really make sense at all.

Anyway not long to wait, seems like 2024 is gonna be a year we all will drown in some Lake.

 

[SlimFan]

No, but it's a stillborn product and given that SRF-AP wasn't on the roadmaps...
Platform readiness lol

Do you mean platform readiness of the Birchstream platform which is common between GNR and SRF?

 

[H433x0n]

I am starting to think, that ARL performance estimates were like being Sierra Forrest 144C only -> designed to weed out rabid leakers.
If it is really on 20A, numbers we were "given" don't really make sense at all.

Anyway not long to wait, seems like 2024 is gonna be a year we all will drown in some Lake.

I hope that’s true but I wouldn’t bet on it. The only way that’s the case is if they can somehow get ARL-S to clock in the neighborhood of 5.4ghz.

 

[adroc_thurston]

Do you mean platform readiness of the Birchstream platform which is common between GNR and SRF?

-AP and -SP are very different things for BHS.