Discussion Intel current and future Lakes & Rapids thread

[csbin]

Sunnycove is Sunnycove.
Icelake is Icelake.

They shouldn't be the same since.. Sunnycove was developed together with Skylake. I assume Sunnycove core has simply acquired up to Icelake ISA compatibility.

Icelake being based on Skylake-SP. Sunnycove being a new core and having a more optimized FPU for SHA-NI(Goldmont/Cannonlake ISA) and VAES(Icelake ISA).

Sunnycove being a 14-nm part, points toward this being a good thing. *shrug* I have previously talked about Sunnycove being 10-nm, but newer NGC leaks say 14-nm and 7-nm only.

Sunnycove -> No server part
WLcove -> Sapphire Rapids
Oceancove -> Granite Rapids

Sunnycove is Code Name
Ice lake is Architecture Name

 

[Bouowmx]

"Sunny cove" is name of architecture, processor family, or platform? First time I have heard of the name.

woops. posted this after 'csbin' elaborated.

 

[NostaSeronx]

Sunnycove is Code Name
Ice lake is Architecture Name

"Sunny cove" is name of architecture, processor family, or platform? First time I have heard of the name.

They are both architectural code names for given processors within a set platform.

Icelake becomes Icelake-U, etc. Icelake-U utilizes Icelake cores.
Sunnycove becomes Sunnycove-U, etc. Sunnycove-U utilizes Sunnycove cores.

The cove cores come from an arduously developed new architecture derived from a cancelled Itanium project. Which isn't related to Icelake in anyway other than ISA compatibility.

Sunnycove core => Folsom/SoftMachines(Also, Folsom)
Icelake core => Oregon/Haifa

 

[csbin]

They are both architectural code names for given processors within a set platform.

Icelake becomes Icelake-U, etc. Icelake-U utilizes Icelake cores.
Sunnycove becomes Sunnycove-U, etc. Sunnycove-U utilizes Sunnycove cores.

The cove cores come from an arduously developed new architecture derived from a cancelled Itanium project. Which isn't related to Icelake in anyway other than ISA compatibility.

Sunnycove core => Folsom/SoftMachines(Also, Folsom)
Icelake core => Oregon/Haifa

 

[csbin]

They are both architectural code names for given processors within a set platform.

Icelake becomes Icelake-U, etc. Icelake-U utilizes Icelake cores.
Sunnycove becomes Sunnycove-U, etc. Sunnycove-U utilizes Sunnycove cores.

The cove cores come from an arduously developed new architecture derived from a cancelled Itanium project. Which isn't related to Icelake in anyway other than ISA compatibility.

Sunnycove core => Folsom/SoftMachines(Also, Folsom)
Icelake core => Oregon/Haifa

so


https://www.anandtech.com/show/13699/intel-architecture-day-2018-core-future-hybrid-x86/4

 

[NostaSeronx]

so

Tejas Nehalem and Core Nehalem scenario. I guess?

https://images.anandtech.com/doci/13699/1-Roadmap.jpg

Sunnycove => Sunny Cove
WLcove => WilLow Cove (biggest mystery solved and this is the huge ultra-wide core)
Oceancove must be after Golden Cove. Which will probably have transistor optimization as Willow Cove.

Sunnycove is in Icelake. Not Icelake is in Sunnycove.

On another side note for the future.. as the cove series progress. More Cluster-based Multithreading architecture tweaks should be apparent.

 

[csbin]

Tejas Nehalem and Core Nehalem scenario. I guess?

https://images.anandtech.com/doci/13699/1-Roadmap.jpg

Sunnycove => Sunny Cove
WLcove => WilLow Cove (biggest mystery solved and this is the huge ultra-wide core)
Oceancove must be after Golden Cove. Which will probably have transistor optimization as Willow Cove.

Sunnycove is in Icelake. Not Icelake is in Sunnycove.

On another side note for the future.. as the cove series progress. More Cluster-based Multithreading architecture tweaks should be apparent.

https://www.servethehome.com/first-pictures-of-intel-ice-lake-xeon-server-chips/

 

[Arachnotronic]

Ice Lake is SoC name, Sunny Cove is CPU core name.

 

[Arachnotronic]

They are both architectural code names for given processors within a set platform.

Icelake becomes Icelake-U, etc. Icelake-U utilizes Icelake cores.
Sunnycove becomes Sunnycove-U, etc. Sunnycove-U utilizes Sunnycove cores.

The cove cores come from an arduously developed new architecture derived from a cancelled Itanium project. Which isn't related to Icelake in anyway other than ISA compatibility.

Sunnycove core => Folsom/SoftMachines(Also, Folsom)
Icelake core => Oregon/Haifa

This is all entirely wrong. "Cove" is just the name of the CPU cores, even Cannon Lake's CPU core was a "Cove" and I bet Skylake's core was, too.

Lakes = SoC names.
Coves = Core names.

Every Intel IP has its own code name.

 

[IntelUser2000]

This is all entirely wrong. "Cove" is just the name of the CPU cores, even Cannon Lake's CPU core was a "Cove" and I bet Skylake's core was, too.

Nosta should stop believing the visions he's having. Tell them to go away. They don't actually have deep secret infos to tech companies.

He really knows how to tickle your fancy though. I rooted for you Nosta, honest. I wanted you to be right about the post Goldmont Plus cores. But when information keeps being wrong, you have to say enough is enough.

Arachnotronic: What's interesting from the core code-name unveil was that they are going to decouple the core and process in a way.

 

[Arachnotronic]

Nosta should stop believing the visions he's having. Tell them to go away. They don't actually have deep secret infos to tech companies.

He really knows how to tickle your fancy though. I rooted for you Nosta, honest. I wanted you to be right about the post Goldmont Plus cores. But when information keeps being wrong, you have to say enough is enough.

Arachnotronic: What's interesting from the core code-name unveil was that they are going to decouple the core and process in a way.

Yeah. It's pretty telling that they gave core IP roadmaps and didn't tie them to process technologies. That's the way ARM has been doing it for years and it's high time Intel do the same, if only to be sure to have backup plans in case the original target node isn't ready.

 

[IntelUser2000]

The bad thing about this is that its really all about the future. Nothing saying like "Surprise, our next desktop enthusiast chip may be 14nm, but with this new direction it means it uses Sunny Cove cores".

I'm not excited for Sunny Cove. I like what they go for in Lakefield, and it also being the first to use Foveros. Foveros isn't a mere copy of the chiplet design AMD is pursuing. Actually, these choices take several years.

The interposer is the PCH in Foveros. The next step in integration while keeping the flexibility of MCMs.

 

[Eug]

I’m still very confused about the names.

The next 15 W chips are Ice Lake U and use Sunny Cove? All 10 nm?

What about the Y series?

I read a bit in the AnandTech article about Thunderbolt 3. Is that integrated in Ice Lake? What about Ice Lake Y? It was pretty vague in the article.

 

[Yotsugi]

The next 15 W chips are Ice Lake U and uses Sunny Cove? All 10 nm?

Yes and yes, Sunny Cove is the uArch name, Icelake is the implementation name.

What about the Y series?

4+2, same as ICL-U, was leaked ages ago.

 

[jpiniero]

At this point, I do still expect Icelake U/Y to be lowish volume but wider availability than Cannonlake for sure. I am expecting the volume even in 2020 to be mostly Comet and Whiskey.

 

[Yotsugi]

At this point, I do still expect Icelake U/Y to be lowish volume but wider availability than Cannonlake for sure. I am expecting the volume even in 2020 to be mostly Comet and Whiskey.

I'd except some decent mobile 10nm volume for H1 2020, but servers and DT, duh.

 

[jpiniero]

I'd except some decent mobile 10nm volume for H1 2020, but servers and DT, duh.

If that NUC roadmap leak was completely legit, they aren't even doing an Icelake NUC in 2020. Just Comet and Whiskey for Core. Figure the Icelake volume will go to HP and Dell and Lenovo as an option on some laptop models but that's about it.

 

[Yotsugi]

If that NUC roadmap leak was completely legit, they aren't even doing an Icelake NUC in 2020. Just Comet and Whiskey for Core. Figure the Icelake volume will go to HP and Dell and Lenovo as an option on some laptop models but that's about it.

NUCs kind of live in a different world so guessing Intel's actual roadmap is tricky.

 

[Eug]

Yes and yes, Sunny Cove is the uArch name, Icelake is the implementation name.

4+2, same as ICL-U, was leaked ages ago.

Ok thx. So Cannon Lake is effectively dead then? Low volume near-demo parts don’t count.

And TB3?

 

[Yotsugi]

So Cannon Lake is effectively dead then?

It was never alive to begin with.

And TB3?

No idea.
I think it's still part of the PCH.

 

[jpiniero]

The TB3 would be on the PCH. They would have to increase the bandwidth between the PCH and processor however, but that is doable.

 

[Eug]

Yes and yes, Sunny Cove is the uArch name, Icelake is the implementation name.

4+2, same as ICL-U, was leaked ages ago.

It was never alive to begin with.

No idea.
I think it's still part of the PCH.

The TB3 would be on the PCH. They would have to increase the bandwidth between the PCH and processor however, but that is doable.

So is it reasonable to predict:

Ice Lake Y in 2019 H2, maybe with Thunderbolt 3?

 

[Yotsugi]

Ice Lake Y in 2019 H2, maybe with Thunderbolt 3?

Yes!

 

[Eug]

Here’s hoping for that quad Y next year... Mind you I was planning on buying quad 10 nm Y with Thunderbolt in 2016-2017. After Intel’s roadmap collapsed, I bought dual-core Y withhout TB in 2017.

I’ll be keeping my existing dual-core Y laptop at least for a few more years. It turns out TB support hasn’t been a critical issue for me.

 

[mikk]

Other improvements include a new HEVC Quick Sync Video engine that provides up to a 30% bitrate reduction over Gen9 (at the same or better visual quality)

For the media block, Intel says that the Gen11 design includes a ground up HEVC encoder design, with high quality encode and decode support.

https://www.tomshardware.com/reviews/intel-sunny-cove-gen11-xe-gpu-foveros,5932-3.html
https://www.anandtech.com/show/13699/intel-architecture-day-2018-core-future-hybrid-x86/3


One of the most interesting things for me, a new HEVC encoder with better quality.