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Discussion Intel current and future Lakes & Rapids thread

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jpiniero

Diamond Member
Oct 1, 2010
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You know, Lakefield could be Intel's first 10 nm HVM product. There haven't been any rumors about how many Tremont cores it might have, I guess it would be 4, but it would have way less EUs than 64. So it should be decently smaller than QC Icelake U/Y.
 

IntelUser2000

Elite Member
Oct 14, 2003
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Lakefield should be later, because Icelake and Tremont needs to be available for Lakefield to happen.

Besides, Icelake U/Y should be fall of next year.

GT0 for exist
GT0 can go into headless IoT devices, or a micro network node.
 

DrMrLordX

Lifer
Apr 27, 2000
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Wait, Intel is going to produce a die with Core and Atom cores sharing space? I guess Tremont is the successor to Goldmont?

We live in strange times.
 

jpiniero

Diamond Member
Oct 1, 2010
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Wait, Intel is going to produce a die with Core and Atom cores sharing space? I guess Tremont is the successor to Goldmont?

We live in strange times.
Yeah. It's big.LITTLE Intel style, with the big being Icelake. I guess we will see what markets they attempt to sell it to but I imagine it will include Intel's LTE modem on package.
 

DrMrLordX

Lifer
Apr 27, 2000
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Yeah. It's big.LITTLE Intel style, with the big being Icelake. I guess we will see what markets they attempt to sell it to but I imagine it will include Intel's LTE modem on package.
You know, it would be a compelling and interesting product if Intel could execute a product like this on 10nm or 7nm instead of 14nm++(+?). Leading-edge process, Intel's famous power manage ment/boost management (which is often much more robust than what you find in ARM chips), AND big.LITTLE? That's a dizzying array of different power consumption levels you can choose just from one die. For their sake, let's hope they can do this on 10nm.
 
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Dayman1225

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You know, it would be a compelling and interesting product if Intel could execute a product like this on 10nm or 7nm instead of 14nm++(+?). Leading-edge process, Intel's famous power manage ment/boost management (which is often much more robust than what you find in ARM chips), AND big.LITTLE? That's a dizzying array of different power consumption levels you can choose just from one die. For their sake, let's hope they can do this on 10nm.
The product is built on 10nm
 
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jpiniero

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A Tremont core is likely very small - If Lakefield's big.LITTLE is a success, you should assume that big.LITTLE will be expanded to the entire mainstream lineup later, if only for marketing reasons.
 

french toast

Senior member
Feb 22, 2017
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I heard about this a couple of years ago, looks like a really good idea, to think Intel was slagging off ARM back in the day for big_LITTLE...if you can't beat them, join them!.
 

jpiniero

Diamond Member
Oct 1, 2010
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I heard about this a couple of years ago, looks like a really good idea, to think Intel was slagging off ARM back in the day for big_LITTLE...if you can't beat them, join them!.
PR aside, the reason Intel didn't really bother until now was because Windows had no support for big.LITTLE. MS has apparently fixed this.
 

french toast

Senior member
Feb 22, 2017
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PR aside, the reason Intel didn't really bother until now was because Windows had no support for big.LITTLE. MS has apparently fixed this.
How do you know that was the real reason? Android certainly did and intel threw away billions into it before throwing in the towel.

I would have to assume they didn't because they couldn't, at least until 10nm.
 

.vodka

Golden Member
Dec 5, 2014
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https://www.reddit.com/r/intel/comments/9o8o55/cannon_lake_review/

Looks like we've got the first i3 8121u review in the form of a reddit post.

VERY interesting and complete writeup.

Conclusion
The NUC8i3CYSM ($574) is a mediocre product, and the i3-8121U is a mediocre chip. Nevertheless, they represent the first, and possibly only, availability of Cannon Lake for microarchitecture enthusiasts. As shown, the improvements to Cannon Lake blur the lines between "tick" and "tock," adding a new instruction set in AVX-512, new LPDDR4 memory controllers, as well as general improvements to front-end and back-end. Indeed, mere "shrinks" have often come with significant IPC gains in the past, as the first version of a new architecture often comes with bugs that require performance-improving features to be disabled. For example, the Ivy Bridge microarchitecture enables MOV-elimination in the front-end and a cycle-aware L3 cache, features that were likely intended for Sandy Bridge.
There seems to be an IPC increase, reminiscent of what Sandy -> Ivy was.

On the other hand, here's the star of the show:

Test Protocol
The NUC8i3CYSM will be compared against a Dell XPS 13 9350 featuring a "Skylake" i7-6500U, which operates at a similar frequency to the i3-8121U. The XPS 13 has been undervolted to enable it to run at its maximum turbo frequency under all workloads. The NUC's power limits were increased to 30 W for the same reason. Unless otherwise mentioned, benchmarks do not use AVX-512 instructions. All benchmarks are run multiple times, and the highest score is reported.


10 nm Process Technology
Intel's 10 nm process technology was expected to reduce power (dynamic capacitance) and increase performance (drive current), when compared to the original 14 nm process. To assess this, power metrics were monitored during CineBench execution via HWiNFO. For this test, the voltage of the i7-6500U was restored to factory values.



The capacitance reduction of 10 nm is evident, as the minimally binned i3-8121U has a 10% efficiency gain over the "i7"-grade 6500U, despite having a 100 mV penalty. Unfortunately, the same voltage penalty shows that the performance benefits of 10 nm are not being realized in the i3-8121U. Since the launch of "Skylake," Intel has released "Kaby Lake" and "Coffee Lake" processors on enhanced 14 nm processes, which improve drive current and hence allow operation at lower voltages. These 14 nm performance improvements also translate to power reduction, so 10 nm as it currently stands is not ready for widespread adoption.

That's 10nm vs first gen 14nm, and the 8121u running in a NUC.... hilariously bad. 14++ or 8C Coffeelake's iteration is probably light years ahead in most metrics, save for density.



It really puts this into perspective:



That has to be an overly optimistic comparison of 14nm v1 vs 10nm.
 
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jpiniero

Diamond Member
Oct 1, 2010
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I dunno, NBC's review of the Aspire with the 8130U got 338, and in the review they mention it was staying between 3.1 and 3.2. That has single channel DDR4 2400 memory.
 

Gideon

Golden Member
Nov 27, 2007
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So based on current info and leaks, it seems that Cannon-Lake brought up to 6% improvement in some vectorised workloads, while Ice-Lake will at least bring some improvements in Hyper-threading.
 
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IntelUser2000

Elite Member
Oct 14, 2003
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So based on current info and leaks, it seems that Cannon-Lake brought up to 6% improvement in some vectorised workloads, while Ice-Lake will at least bring some improvements in Hyper-threading.
Hold that thought. Since its measured using Turbo mode, it will deviate a few % from the 6%. It may not be 6%, but 2% for example. The AVX comparisons and the explanations are very good though. We won't see proper perf/clock comparisons until the chip has Turbo off and set to same frequency.

I dunno, NBC's review of the Aspire with the 8130U got 338, and in the review they mention it was staying between 3.1 and 3.2. That has single channel DDR4 2400 memory.
It's not exactly comparable as the 8130U has higher Turbo.

Don't make conclusions until a proper testing has been done.
 

Dayman1225

Golden Member
Aug 14, 2017
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Ian from Anandtech is testing the Cannon Lake Laptop though I am not sure when it is meant to come out.
 

TheGiant

Senior member
Jun 12, 2017
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So what is the IPC difference? do we have any serious numbers? how come that no one can publish the cannon lake benches....
 

Dayman1225

Golden Member
Aug 14, 2017
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So what is the IPC difference? do we have any serious numbers? how come that no one can publish the cannon lake benches....
Because Intel didn't sample it to reviewers so they must be bought by themselves. Though like I said Ian from Anandtech is working on a review.
 

DrMrLordX

Lifer
Apr 27, 2000
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Sorry but is this part a complete joke? Arm SoCs are years ahead in this regard.
No. ARM took a pass on power gating (to the extent that Intel pushes it) and just went big.LITTLE. Intel tries to have one core (or a small set of cores) in their low-power chips scale from boosted 3 GHz+ states chewing up higher-than-TDP power ratings to ultra-low clockspeeds with sub-4.5W power usage. And to their credit, it almost worked. But they have never been able to make Core suitable for tablets or phones, and it will never work. Atom didn't work out there either, nor will it ever. Which is why they punted on those markets, at least for awhile.

Lakefield may (eventually) change that.
 

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