- Jun 1, 2017
Good call. Reminder we are still in a pandemic situation that effects shipments even at a very basic level. And if TSMC is affected by shipment delays of EUV equipment by ASML due to the current circumstances chances are Intel is as well.We don't yet know the reason why N3 broke TSMC's cadence. It might have been due to issues getting the process to work, or it might have been issues related to sufficient delivery of EUV scanners. After all, TSMC has been expanding N7+/N6 wafer starts which use a limited amount of EUV, and is in the process of expanding N5/N4 wafer starts which use even more EUV. N3 will reportedly use EUV for over 20 layers and they have some pretty aggressive targets even for risk production (30k wpm) let alone the first phase of mass production (105k wpm) If it is the latter ASML does look to be making progress with increasing yearly shipments so it may not be too much of a gating factor. I guess the wildcard is how heavily DRAM fabs get into EUV.
Before worrying that Intel may be "stuck" at Intel 4, how about worrying that they can actually get there in the promised timeline? They haven't exactly been good at keeping their promises for the past half dozen years, and all the while were saying they were on track and claiming just temporary delays.