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Discussion Intel current and future Lakes & Rapids thread

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Hulk

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Oct 9, 1999
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Power constraints, possibly. Alder Lake-S might have been unconstrained on power usage while the Alder Lake-P sample might have been stuck within a particular power envelope.
Yes of course that could be the reason. But it looks nonsensical when written out.

8 Golden Cove + 8 Gracemont > 16 Zen 3

6 Golden Cove + 8 Gracemont < 8 Zen 3
 
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AMDK11

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Jul 15, 2019
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Recently, someone on reddit by the username of mooreslawisnotdead posted an Intel roadmap all the way through 2025. This roadmap contains some products/code names that haven't been mentioned here before. The roadmap could be completely genuine or a total work of fan fiction. I guess that's for you to decide. The user has since deleted his account, but not before I copied this information. What follows is the roadmap itself, along with commentary by the reddit user that posted it:

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Alder Lake (Golden Cove/Gracemont) Q4'21 / Q1'22 - predicted to be competitively weak vs AMD/Apple offerings that time.
Raptor Lake (Raptor Cove / Gracemont) Q3'22 / Q4'22 - 10% CPU perf boost and 8/16 configuration puts intel back on par but expect AMD/Apple to refresh their products as well.
Meteor Lake (Redwood Cove / Crestmont) Q2'23 - Intel's first true chiplet or tile based design. Different dies built on TSMC / Intel processes. More of a node shrink with single digit performance improvements. AMD will again extend lead with Zen 4+ / 5.
Arrow Lake (Lion Cove / Skymont) Q4'23 - Will feature an updated compute tile with 8/32 config for the high end enthusiast products. Might achieve parity with AMD offerings at the time but loses out to Apple in power efficiency.
Lunar Lake (Lion Cove / Skymont) Q4'24 - This is the product that will use TSMC 3nm as reported by Nikkei. Big performance jump expected and designed to achieve parity or beat AMD and Apple in both performance and power efficiency.
Nova Lake (Panther Cove [tentative]/ Darkmont) 2025 - This will mark the biggest architectural change in cpu architecture since the Core architecture is introduced in 2006. Intel is working to build an entirely new architecture from the ground up much like Ryzen with up to 50% cpu performance improvement from lunar lake. This is also the reason why Glenn Hinton returned.
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First of all, Conroe (Core 2) wasn't some big breakthrough at all that was exaggerated to the point of absurdity because it was a natural development from generation to generation x86 microarchitecture from Pentium III through Banias and Yonah to Conroe.

Pentium III
Banias - Pentium M
Yonah - Core M, Core
Conroe - Core 2

Indeed, in desktops between Pentium III and Conroe (Core 2), Netbrust (Pentium 4) reigned supreme, which, despite a much lower IPC, but thanks to the high clock speed, was not so bad compared to the K7 AthlonXP or even the K8 Athlon64. He successfully competed with them. Netbrust was about to get the highest possible clock speed and with these 3.7 GHz high clock speeds it competed quite well with the K8 Athlon64. Conroe or Core 2 in IPC was ahead of K8 Athlon64 even by 25% but with an average of ~ 17%, which is practically as much more as SunnyCove compared to Skylake. Especially that IPC Yonah (Core) was more or less at the level of K8 Athlon64 and the problem was the lower maximum clock speed, which could not make an equal fight. Intel decided that it was still not enough for competition, but under Yonah in the form of Core M there were special motherboards for desktop computers.

Second thing is to ignore the latest Alderlake test leak in CB R20 in which GoldenCove achieves 20 +% higher IPC than Zen3, 30% higher than SunnyCove and 52% higher than Skylake or found it to be false. This alleged Intel plan is bogus or the CB test is bogus. One of the two. Time will show what is closer to the truth.
 
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Gideon

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Nov 27, 2007
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Are people so feeble minded they honestly believe 14 core Alder Lake will have worse performance than Tiger Lake?

I could understand believing it's only a tiny upgrade but way slower than 45W Tiger Lake also in single thread?

Just try some common sense.

This obviously is either early silicon, or something some software/firmware issue.
 

yuri69

Member
Jul 16, 2013
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Second thing is to ignore the latest Alderlake test leak in CB R20 in which GoldenCove achieves 20 +% higher IPC than Zen3, 30% higher than SunnyCove and 52% higher than Skylake or found it to be false. This alleged Intel plan is bogus or the CB test is bogus. One of the two. Time will show what is closer to the truth.
If intel goes all-in with the Golden Cove, it might hit that 30% IPC gain vs Sunny Cove. The frequency seems to stay at 5+GHz and the 10nm process is expected be marginally improved. So why not?

AMD managed 20% with Zen 3 on the same process and frequency.

Besides, Intel is not shy of high TDP nor spending a large portion of the die area on CPU cores.
 
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mikk

Diamond Member
May 15, 2012
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Recently, someone on reddit by the username of mooreslawisnotdead posted an Intel roadmap all the way through 2025. This roadmap contains some products/code names that haven't been mentioned here before. The roadmap could be completely genuine or a total work of fan fiction. I guess that's for you to decide. The user has since deleted his account, but not before I copied this information. What follows is the roadmap itself, along with commentary by the reddit user that posted it:

---------------------------------------------------------------------------------------------
Alder Lake (Golden Cove/Gracemont) Q4'21 / Q1'22 - predicted to be competitively weak vs AMD/Apple offerings that time.
Raptor Lake (Raptor Cove / Gracemont) Q3'22 / Q4'22 - 10% CPU perf boost and 8/16 configuration puts intel back on par but expect AMD/Apple to refresh their products as well.
Meteor Lake (Redwood Cove / Crestmont) Q2'23 - Intel's first true chiplet or tile based design. Different dies built on TSMC / Intel processes. More of a node shrink with single digit performance improvements. AMD will again extend lead with Zen 4+ / 5.
Arrow Lake (Lion Cove / Skymont) Q4'23 - Will feature an updated compute tile with 8/32 config for the high end enthusiast products. Might achieve parity with AMD offerings at the time but loses out to Apple in power efficiency.
Lunar Lake (Lion Cove / Skymont) Q4'24 - This is the product that will use TSMC 3nm as reported by Nikkei. Big performance jump expected and designed to achieve parity or beat AMD and Apple in both performance and power efficiency.
Nova Lake (Panther Cove [tentative]/ Darkmont) 2025 - This will mark the biggest architectural change in cpu architecture since the Core architecture is introduced in 2006. Intel is working to build an entirely new architecture from the ground up much like Ryzen with up to 50% cpu performance improvement from lunar lake. This is also the reason why Glenn Hinton returned.
---------------------------------------------------------------------------------------------

Most of the code names are new, even Crestmont is new to me. Arrow Lake 1 year after Rapor Lake implies to me this is the desktop successor for Raptor Lake and no Meteor Lake for desktop as expected, at least not in 2023. Of course there are so many new code names and even the one after Lunar Lake it could be fan fiction. Time will tell.
 

IntelUser2000

Elite Member
Oct 14, 2003
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Conroe or Core 2 in IPC was ahead of K8 Athlon64 even by 25% but with an average of ~ 17%, which is practically as much more as SunnyCove compared to Skylake.
There's a big difference. Sunny Cove is less power efficient than Skylake as evidenced by Rocketlake. Also, Sunny Cove merely expands on Skylake. More FP, more decode, more L/S capabilities, more registers, more caches.

Yonah wasn't a big deal either. Pretty much a shrinked Pentium M with double the cores. Maybe 5% faster in single thread?

The architecture in Conroe/Merom brought new ideas.

Exactly. TGL-H 8c doesn't perform all that well with 45W power constraints. ADL-P might have similar problems, especially if the power limit is below 45W for that sample.
What the Geekbench results are saying is that Alderlake is slower than Tigerlake though.

@yuri69 You mentioned "IPC". Neither TDP nor clock speed has to do anything with that. It may end up being 30% faster, but it'll be due to clock and 20% improvement. 30% improvement per clock means it won't need to clock higher to perform 30% higher.

Most of the code names are new, even Crestmont is new to me. Arrow Lake 1 year after Rapor Lake implies to me this is the desktop successor for Raptor Lake and no Meteor Lake for desktop as expected, at least not in 2023. Of course there are so many new code names and even the one after Lunar Lake it could be fan fiction. Time will tell.
The big news here seems to be the deemphasizing of their own process. If Lunar Lake is that much superior to Meteor Lake and Arrow Lake using Intel's 7nm, well then I don't know how they'll ever recover. Maybe this whole going to IDM 2.0 is a show and Intel will stop using their process in most of their cutting edge products.

@Gideon Well, we had slower newer CPUs before. Nothing new. I just don't believe that for Alderlake either and certainly not basing that on Geekbench.
 
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IntelUser2000

Elite Member
Oct 14, 2003
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Again, another thing indicating Gracemont must be fraction of the size of Golden Cove. Tigerlake-H is a 190mm2 die. If you assume Golden Cove is just 25% larger than Willow Cove, then we end up with 210mm2. If it's 50% larger, possibly 230mm2.

Which means if Gracemont is half the size, 8 cores will add another 50 to 70mm2. 16 cores will add 100 to 140mm2. That's 260-280mm2 for Alderlake, and 310-370mm2 for Raptor Lake.

Intel client cores have never exceeded 300mm2. 1/4 size Gracemont will add 25 to 35mm2 for 8 cores, and 50 to 70mm2 for 16 cores.

Even if you assume quarter the size, and Golden Cove only grows by 25%, you end up with a 260mm2 Raptor Lake chip. I'm going to guess it'll end up smaller than 1/4 the size of Golden Cove. Perhaps the core in the 1.2-1.5mm2 range.
 
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jpiniero

Diamond Member
Oct 1, 2010
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Again, another thing indicating Gracemont must be fraction of the size of Golden Cove. Tigerlake-H is a 190mm2 die. If you assume Golden Cove is just 25% larger than Willow Cove, then we end up with 210mm2. If it's 50% larger, possibly 230mm2.

Which means if Gracemont is half the size, 8 cores will add another 50 to 70mm2. 16 cores will add 100 to 140mm2. That's 260-280mm2 for Alderlake, and 310-370mm2 for Raptor Lake.

Intel client cores have never exceeded 300mm2. 1/4 size Gracemont will add 25 to 35mm2 for 8 cores, and 50 to 70mm2 for 16 cores.

Even if you assume quarter the size, and Golden Cove only grows by 25%, you end up with a 260mm2 Raptor Lake chip. I'm going to guess it'll end up smaller than 1/4 the size of Golden Cove. Perhaps the core in the 1.2-1.5mm2 range.
Tiger Lake-H includes the Thunderbolt and IPU, which presumably the Alder Lake S die does not.
 

yuri69

Member
Jul 16, 2013
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You mentioned "IPC". Neither TDP nor clock speed has to do anything with that.
They do - indirectly. Making a design notably wider and/or deeper - increasing IPC - usually requires more power to hit a high target frequency. Clever microarch tricks and advanced lithography mitigate those effects.

This way both frequency and TDP are kinda related.
 

scineram

Member
Nov 1, 2020
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Oh go to hell. I never said Intel was "the devil". Nice projecting. He was a joke at AMD as well. Hell, at least at Intel he didn't say anything too stupid. And what reality? That guy has always been overrated IMO, show me what he has done that is impressive.
RDNA (2) is pretty good, no?
 

Gideon

Golden Member
Nov 27, 2007
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RDNA (2) is pretty good, no?
Raja left AMD in 2017 so he might have some limited influence on RDNA (2019) but not much beyond that. how long are you going to credit him? Till RDNA7?

Besides he was a useless top exec he might have signed something off, but dind't design anything, only hype to ridiculous levels. These execs usually take all of the engineer's credit and none of the blame.
 

eek2121

Golden Member
Aug 2, 2005
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Are people so feeble minded they honestly believe 14 core Alder Lake will have worse performance than Tiger Lake?

I could understand believing it's only a tiny upgrade but way slower than 45W Tiger Lake also in single thread?

Just try some common sense.

This obviously is either early silicon, or something some software/firmware issue.
There's a big difference. Sunny Cove is less power efficient than Skylake as evidenced by Rocketlake. Also, Sunny Cove merely expands on Skylake. More FP, more decode, more L/S capabilities, more registers, more caches.

Yonah wasn't a big deal either. Pretty much a shrinked Pentium M with double the cores. Maybe 5% faster in single thread?

The architecture in Conroe/Merom brought new ideas.



What the Geekbench results are saying is that Alderlake is slower than Tigerlake though.

@yuri69 You mentioned "IPC". Neither TDP nor clock speed has to do anything with that. It may end up being 30% faster, but it'll be due to clock and 20% improvement. 30% improvement per clock means it won't need to clock higher to perform 30% higher.



The big news here seems to be the deemphasizing of their own process. If Lunar Lake is that much superior to Meteor Lake and Arrow Lake using Intel's 7nm, well then I don't know how they'll ever recover. Maybe this whole going to IDM 2.0 is a show and Intel will stop using their process in most of their cutting edge products.

@Gideon Well, we had slower newer CPUs before. Nothing new. I just don't believe that for Alderlake either and certainly not basing that on Geekbench.
From what I gather, the Golden Cove cores were locked to 800 Mhz thanks to bugs for all leaks. (maybe Intel did this intentionally?)
 

JoeRambo

Golden Member
Jun 13, 2013
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There's a big difference. Sunny Cove is less power efficient than Skylake as evidenced by Rocketlake. Also, Sunny Cove merely expands on Skylake. More FP, more decode, more L/S capabilities, more registers, more caches.

Yonah wasn't a big deal either. Pretty much a shrinked Pentium M with double the cores. Maybe 5% faster in single thread?

The architecture in Conroe/Merom brought new ideas.
Conroe was big deal, cause it enlarged OoO big time, added actual additional execution ports and widened the machine to 4 decode / 4 rename /4 dispatch. All these used to be 3-wide in previuos P6 based CPUs.
Massive step forward that caught AMD with pants down. While Sunny Cove was meh even for ~2017 era it was meant to appear in. Derivative of Skylake, that used 10nm density gains to blow transistors on OoO and AVX512 exec units/registers. Kinda only real innovation that they did was dual store ports, i think first for x86 CPUs. Good derivative of Skylake for 2017.

Golden Cove is gonna be first Intel core design after long years, 20% IPC gain versus Sunny Cove is not that big of achievement after considering the fact that they had extra 3+ years to design it and frankly generations of Apple and AMD designs to draw new ideas from.

EDIT: some predictions of what Intel is gonna do with Golden Cove, beyond traditional "larger" OoO resources and improved branch prediction:

1) 0 bubble BPU - pretty much obvious, even the best branch prediction in the world would be 2 cycles slower than AMD for predicted taken branches
2) 6 uOps from decode OR more tricks in decode stage like what apple does with op elimination before they even move further into frontend
3) One more ACTUAL execution port. Core went to 3 ports, Haswell increased to 4 and Intel has lived with 4 since then. Piling transistors on ports is not the same as having a 5th one. AMD has 8 independant pipes in Int/FP and from Cinebench results i am almost certain we got 5th port and proper increase in dispatch / retirement
4) 3 loads are very likely, since it has been 10+ years since Sandy Bridge was designed and even AMD has moved to 3 load ports now.

And this all has interesting sideeffect of probably being underutilized and increasing HT gains for Intel.
 
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scineram

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Raja left AMD in 2017 so he might have some limited influence on RDNA (2019) but not much beyond that. how long are you going to credit him? Till RDNA7?

Besides he was a useless top exec he might have signed something off, but dind't design anything, only hype to ridiculous levels. These execs usually take all of the engineer's credit and none of the blame.
Not crediting him more than any other executive. His job was to oversee the development of Vega, RDNA, maybe CDNA. Those are definitely impressive, with RDNA addressing the shortcomings of GCN. That is all.
 

A///

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Feb 24, 2017
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Sunnycove inefficiencies are a result of Rocketlake being a backport AFAIK. Alderlake P reports being in, which I suspect is what we're all discussing since this thread's been on a frenzy the last day or two, is disappointing but because it's not a Windows 11 test. There's been a lot of talk about the Windows 11 scheduler being next-gen and helping all processors, but especially hybrid ones. Yet it was touted that Intel's hardware based scheduler would do the heavy lifting. At this point I'm going to take any Intel and AMD rumor with a planet full of salt because there's no point in placing your faith in either company's next big achievement when all we have to go on are mere whispers parlayed as leaks.

Leave you love for one company at the door, and pray they both one up each other for the foreseeable future. Not only does the customer win on better hardware each generation, but they win on price, too.

/Yoda out.
 
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itsmydamnation

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Feb 6, 2011
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Sunnycove efficiencies are a result of Rocketlake being a backport AFAIK.
But thats what was meant , both from Zen1 to Zen 2 and Zen2 to Zen3 AMD improved perf/power process agnostic.
ARM has done this many times the big obvious one was A57 to A72
 

A///

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Feb 24, 2017
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But thats what was meant , both from Zen1 to Zen 2 and Zen2 to Zen3 AMD improved perf/power process agnostic.
ARM has done this many times the big obvious one was A57 to A72
I've spent 10 minutes wondering what the heck you were trying to say when I noticed my own error. Not efficiencies, but inefficiencies. Mind was concentrating on the TV program I was watching. I've edited my post to make my point clearer.
 

Thunder 57

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Not crediting him more than any other executive. His job was to oversee the development of Vega, RDNA, maybe CDNA. Those are definitely impressive, with RDNA addressing the shortcomings of GCN. That is all.
I don't want to get off topic here but how much did he really have to do with RDNA? Also, I didn't think much of discrete Vega. It does well enough as a low power APU part (that is certainly showing its age), but in the desktop I never thought much of it.

I think Polaris was more impressive which still sees a good amount of use to this day. Vega 56 was OK, Vega 64 wasn't much better and used a lot more power, and Vega VII was basically a pipecleaner that did well in compute but was pricy and not very impressive for gaming by the time it came out.

RDNA onwards have faired much better. It's incredible to see how much better my RX 5700 performs compared to my RX 480 considering they have the same number of CU's. Apparently it suffered from serious driver issues but by the time I got mine that was all sorted out.
 
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DrMrLordX

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There's a big difference. Sunny Cove is less power efficient than Skylake as evidenced by Rocketlake.
The quote you attributed to me was someone else's ( @AMDK11 ) . Not sure how that happened. Moving right along:

What the Geekbench results are saying is that Alderlake is slower than Tigerlake though.
Okay that was me you were quoting there. And yes, if the AlderLake-P sample has a substantially lower power budget, then yes AlderLake-P could easily have lower performance than TigerLake-H. Though it would have to be a low power budget for AlderLake-P to be slower in the ST test.
 

lobz

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Feb 10, 2017
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I've spent 10 minutes wondering what the heck you were trying to say when I noticed my own error. Not efficiencies, but inefficiencies. Mind was concentrating on the TV program I was watching. I've edited my post to make my point clearer.
But then... Sunny Cove was never a backport, it was designed for 10nm and stayed on 10nm for Ice Lake. I don't understand your comment about its inefficiencies having to do anything with Rocket Lake.
 
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coercitiv

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Alderlake P reports being in [...] is disappointing but because it's not a Windows 11 test. There's been a lot of talk about the Windows 11 scheduler being next-gen and helping all processors, but especially hybrid ones. Yet it was touted that Intel's hardware based scheduler would do the heavy lifting.
This "magical" scheduler talk needs to stop. The scheduler does not do "heavy lifting", it has only one job, which is to minimize performance loss. In the case of benchmarks such as CB, GB, Passmark - the scheduler's job is extremely simple: puts the ST test on a big core, puts the MT test on all cores. It doesn't get more basic than that.

Moreover, it has been repeatedly explained in this thread that Microsoft already has a hybrid scheduler - which is also available in Win 10. Whether MS and Intel have worked to fine-tune this scheduler for Win 11 /w Alder Lake to extract more efficiency in complex real-world scenarios that are not synthetic benchmarks with very scalable workloads, that remains to be seen, but even then don't imagine big jumps in efficiency because the bulk of the effort was done years ago already.

Windows 10 Scheduler Aware of "Lakefield" Hybrid Topologies
The Golem.de report reveals that Windows 10 thread scheduler is aware of the hybrid multi-core topology of "Lakefield," and that it is able to classify workloads at a very advanced level so the right kind of core is in use at any given time. The "Sunny Cove" core is called upon when interactive vast serial processing loads are in demand. This could even be something like launching applications, new tabs in a multi-process web-browser, or less-parallelized media encoding. The four "Tremont" cores keep the machine "cruising," handling much of the operational workload of an application, and is also better tuned to cope with highly parallelized workloads.
1627282499754.png

Throughout Golem's testing, they observed that the "Sunny Cove" core kicks in during interactive workloads that require burst performance from the CPU, with the core typically clocked at 2.50 GHz, occasionally hitting 2.90 GHz. The smaller "Tremont" cores are typically clocked at 1.90 GHz during workloads, and can boost up to 2.70 GHz.
Perhaps the biggest dividend of topology-awareness by Windows OS scheduler is with the core rotation policy. By default, the Windows scheduler spreads a single-threaded workload across multiple cores (in sequence). AMD had to work with Microsoft to make Windows aware of the topology of its multi-CCX Ryzen processors, so workloads aren't spread between two CCX's if they don't have to. Similarly with "Lakefield," core rotation is localized to the "Tremont" cores.
 

Thala

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This "magical" scheduler talk needs to stop. The scheduler does not do "heavy lifting", it has only one job, which is to minimize performance loss. In the case of benchmarks such as CB, GB, Passmark - the scheduler's job is extremely simple: puts the ST test on a big core, puts the MT test on all cores. It doesn't get more basic than that.
Right - i wonder how often this has to be repeated. In your examples above (e.g. synthetic benchmarks) even a non hybrid-aware scheduler would find the optimum schedule, because the solution is so trivial - as you perfectly describe. Even sophisticated performance counters will not give any insights to change the schedule in these cases, because the schedule is already optimal.
The more interesting cases for a hybrid scheduler are the non-trivial cases, where the system is only partially loaded with complex dependencies between threads.
 
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