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Discussion Intel current and future Lakes & Rapids thread

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eek2121

Golden Member
Aug 2, 2005
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Just like Ice Lake SP launched last year you mean?

For the record this is how Intel sees the timeline more recently:
The most recent data I've seen shows Sapphire Rapids launching with Alder Lake. How old is that slide? The information I have is from early April. Sapphire Rapids will NOT replace Ice Lake SP. Both will be sold. Sapphire Rapids is close to final silicon, so I do not expect there to be much of a delay, if any. It also does not matter, because I am almost certain it will be out well before Zen 4 (if the Zen 4 leaks are accurate, which they probably are).

Intel will be moving as quickly as possible to move all their 10nm nodes to 10ESF so they can increase capacity. Typical Intel product lines are long lived, so the sooner they get off their old non-SF/non-ESF the better. There is also another 10nm enhancement beyond ESF.

As an FYI, 3 examples where Sapphire Rapids or Alder Lake running DDR5 would immediately trounce AMD are:
  1. Redis and other in-memory stores.
  2. Cloud compute provides (which typically host everything in #1 along with other memory intensive processes)
  3. Video Encoding
EDIT: My information came directly from a top 5 OEM.
 
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uzzi38

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Oct 16, 2019
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Genoa is a year and a half away according to leaks, not months away. Sapphire Rapids is launching this year. It will not be competing with Zen 4, it will be competing with Milan.

If you honestly think Alder Lake S isn't going to compete with the 5950X, you've been living under a rock. Intel is fully capable of building a chip with more Golden Cove cores, yet they don't. Why? They don't need to. It's definitely not because of power, we all know Intel does not care about that. The 8 big cores alone will end up beating the 5900X.



As mentioned above, we keep getting rumors that AMD isn't pushing out Genoa/Zen 4 until a year and a half from now (H2 2022, likely Q4). Zen 4 won't be competing with Sapphire Rapids, Ice Lake SP, or Alder Lake. It will be competing against their successors. At that point, assuming Intel has no further delays with 7nm (lol yeah right), Intel will be just months away from launching it's first 7nm products. Basically they both will remain in lockstep from a process perspective. AMD will not have a lead on the process any longer. They will have to compete purely on the architecture.

EDIT: I think the whole rumored 20% ST perf increase is throwing people off. That doesn't count the introduction of DDR5 and the increases it will bring.
Genoa is not a year and a half away. It's a year and a bit, but not coming right at the end of 2022. There is also a high possibility it is the first Zen 4 part, contrary to prior generations.

Alder Lake-S isn't going to be 50% faster per core Golden Cove vs Zen 3, and I have no clue what makes you think it will be. Not that it matters either way, because I know where it lands relative to Zen 3 in SPEC2017.
 

uzzi38

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Oct 16, 2019
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The most recent data I've seen shows Sapphire Rapids launching with Alder Lake. How old is that slide? The information I have is from early April. Sapphire Rapids will NOT replace Ice Lake SP. Both will be sold. Sapphire Rapids is close to final silicon, so I do not expect there to be much of a delay, if any. It also does not matter, because I am almost certain it will be out well before Zen 4 (if the Zen 4 leaks are accurate, which they probably are).

Intel will be moving as quickly as possible to move all their 10nm nodes to 10ESF so they can increase capacity. Typical Intel product lines are long lived, so the sooner they get off their old non-SF/non-ESF the better. There is also another 10nm enhancement beyond ESF.

As an FYI, 3 examples where Sapphire Rapids or Alder Lake running DDR5 would immediately trounce AMD are:
  1. Redis and other in-memory stores.
  2. Cloud compute provides (which typically host everything in #1 along with other memory intensive processes)
  3. Video Encoding
EDIT: My information came directly from a top 5 OEM.
Intel's official guidance on SPR given at the Q1 earnings is the following:

"We look to enter production around the end of the year, ramping in the first half of 2022". Are you also going to claim that this "data" you speak of outranks Intel's own words as of just a month ago?
 

DrMrLordX

Lifer
Apr 27, 2000
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40 million not 4.
Oh well in that case, I guess the TigerLake-H shipping numbers aren't so great in comparison.

Ian is collecting questions for an interview with Keller, ask him!
Make a separate thread for that, if you haven't already. Really it deserves an organized, separate thread.

We certainly need better reviews. That second slide graphing TDP vs performance is pure garbage. Everybody knows TDP is not the same as power consumption (as you already said).
Let me get this straight. You have the second graph with CPU A having a TDP of 45W and CPU B also having a TDP of 45W at a particular data point. Which I guess implies the people charting data used cTDP or something similar to set the TDP for each chip, and then tested their performance?

CPU A has a TDP "power up" of 65W at a TDP of 45W while CPU B has a "power up" of 54W at the same TDP. CPU B mops the floor with CPU A at that TDP setting.

Do you somehow imagine that the reviewer has been unfair to CPU A? Would you rather they have said, "up to 65W" vs. "up to 54W"? I agree that precise power numbers would have been nice, but I hope you realize, you are not exactly making a strong case for TigerLake-H here.
 
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eek2121

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Aug 2, 2005
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Genoa is not a year and a half away. It's a year and a bit, but not coming right at the end of 2022. There is also a high possibility it is the first Zen 4 part, contrary to prior generations.

Alder Lake-S isn't going to be 50% faster per core Golden Cove vs Zen 3, and I have no clue what makes you think it will be. Not that it matters either way, because I know where it lands relative to Zen 3 in SPEC2017.
Zen 4 desktop Oct/Nov 2022: https://videocardz.com/newz/amd-zen4-raphael-ryzen-cpus-for-desktops-rumored-to-launch-in-q4-2022

Rocket Lake and Zen 3 are tied in 1T spec 2017: https://www.anandtech.com/bench/product/2787?vs=2673

Ice Lake, despite having a slightly lower frequency, is neck in neck with Milan in ST perf: https://www.anandtech.com/show/16594/intel-3rd-gen-xeon-scalable-review/7

Golden Cove will be 20% faster than rocket lake, while being able to boost significantly higher thanks to lower power consumption and improved thermals. SPR and ADL will also support DDR5, which will almost DOUBLE the performance of memory bound applications.

I'm sure in the end he'll just pick a heavy AVX-512 load and claim victory
You are the one trolling an Intel thread with vague assumptions that fly in the face of all the leaks and information we have seen thus far. You also have a history of being pro-AMD/anti-Intel, even when Intel makes a compelling product.
 
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eek2121

Golden Member
Aug 2, 2005
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Oh well in that case, I guess the TigerLake-H shipping numbers aren't so great in comparison.



Make a separate thread for that, if you haven't already. Really it deserves an organized, separate thread.



Let me get this straight. You have the second graph with CPU A having a TDP of 45W and CPU B also having a TDP of 45W at a particular data point. Which I guess implies the people charting data used cTDP or something similar to set the TDP for each chip, and then tested their performance?

CPU A has a TDP "power up" of 65W at a TDP of 45W while CPU B has a "power up" of 54W at the same TDP. CPU B mops the floor with CPU A at that TDP setting.

Do you somehow imagine that the reviewer has been unfair to CPU A? Would you rather they have said, "up to 65W" vs. "up to 54W"? I agree that precise power numbers would have been nice, but I hope you realize, you are not exactly making a strong case for TigerLake-H here.
The chart is useless without having the actual TDP. If I had only seen that chart, I would have called it questionable, but seeing the CB20 numbers makes me wonder if the slide deck is fake.
 

Asterox

Senior member
May 15, 2012
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Genoa is a year and a half away according to leaks, not months away. Sapphire Rapids is launching this year. It will not be competing with Zen 4, it will be competing with Milan.

If you honestly think Alder Lake S isn't going to compete with the 5950X, you've been living under a rock. Intel is fully capable of building a chip with more Golden Cove cores, yet they don't. Why? They don't need to. It's definitely not because of power, we all know Intel does not care about that. The 8 big cores alone will end up beating the 5900X.



As mentioned above, we keep getting rumors that AMD isn't pushing out Genoa/Zen 4 until a year and a half from now (H2 2022, likely Q4). Zen 4 won't be competing with Sapphire Rapids, Ice Lake SP, or Alder Lake. It will be competing against their successors. At that point, assuming Intel has no further delays with 7nm (lol yeah right), Intel will be just months away from launching it's first 7nm products. Basically they both will remain in lockstep from a process perspective. AMD will not have a lead on the process any longer. They will have to compete purely on the architecture.

EDIT: I think the whole rumored 20% ST perf increase is throwing people off. That doesn't count the introduction of DDR5 and the increases it will bring.
No Intel cant do it, and for several reasons this is a real situation.

- 16 big Desktop Golden Cove cores, very large die size=low yields=not competitive and commercially unprofitable
- power consumption outrageous X2
- PL2 performance, hm easy 300+W


If you remember poorly, look how much power can eat 16/32 Zen 3 CPU.Golden Cove cores are to big, and very much power hungry.It is very simple, Zen 3 is much beeter design/more energy efficient CPU arhitecture.


For example, Intel needs a Mobile CPU the is not pushed to hard.PL2 Performance for 8 Core TigerLake H up to 135W, this is absurdly.Intel has no other option, too high Mobile CPU frequencies+green very unexpected competition.

 
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Gideon

Golden Member
Nov 27, 2007
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You are the one trolling an Intel thread with vague assumptions that fly in the face of all the leaks and information we have seen thus far. You also have a history of being pro-AMD/anti-Intel, even when Intel makes a compelling product.
I've been more generous than most AMD fans towards Rocket Lake. I've praised the 6 cores in particular. And all the leaks and info points to Golden Cove having 50% perf per core than Zen3 ?
 

JoeRambo

Golden Member
Jun 13, 2013
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Both Intel and AMD are pushing CPUs way beyond their v/f efficiency points. Intel being so behind in MT even more so. They are both throwing watts to push mhz so to say.

16C Golden Cove clocked to 3.X ghz on reasonable voltage would not consume that much wattage. AMDs ZEN3 clocks ~3.8Ghz when wattage limited under full MT load, so no reason why Intel can't do the same, maybe a bit less mhz, maybe some more watts, but it can be done.
 

coercitiv

Diamond Member
Jan 24, 2014
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Golden Cove will be 20% faster than rocket lake, while being able to boost significantly higher thanks to lower power consumption and improved thermals.
Willow Cove is 18%+ faster per clock over Skylake, yet TGL-H is only 19% faster over Comet Lake when compared at 45W TDP. The jump from 14nm to 10SF brought just enough efficiency to compensate for the larger cores, not enough to allow for even more performance through higher clocks.

Intel-Tiger-Lake-H-Press-Deck-38.jpg
 

uzzi38

Golden Member
Oct 16, 2019
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Zen 4 desktop Oct/Nov 2022: https://videocardz.com/newz/amd-zen4-raphael-ryzen-cpus-for-desktops-rumored-to-launch-in-q4-2022

Rocket Lake and Zen 3 are tied in 1T spec 2017: https://www.anandtech.com/bench/product/2787?vs=2673

Ice Lake, despite having a slightly lower frequency, is neck in neck with Milan in ST perf: https://www.anandtech.com/show/16594/intel-3rd-gen-xeon-scalable-review/7

Golden Cove will be 20% faster than rocket lake, while being able to boost significantly higher thanks to lower power consumption and improved thermals. SPR and ADL will also support DDR5, which will almost DOUBLE the performance of memory bound applications.



You are the one trolling an Intel thread with vague assumptions that fly in the face of all the leaks and information we have seen thus far. You also have a history of being pro-AMD/anti-Intel, even when Intel makes a compelling product.
Is Zen 4 desktop Genoa? Last I checked Genoa was a server part. And I specifically said Genoa was the one that is not Q4, and even stated afterwards that I don't expect Raphael to launch before Genoa.

Rocket Lake clocks at 5.3GHz 1T vs the 4.9GHz rated turbo of the 5950X and performs the same in 1T. Well done, you've pointed out an 8-10% IPC deficit and I didn't even have to do a thing.

Ice Lake being neck and neck vs Milan in 1T performance at the same clocks is to be expected. If anything a bit on the lower side than I'd expect, given the larger L3 cache accessible per core (50MB for ICX vs 32MB for Milan) and ~10ns better memory latency, which are enough to make up for the 100MHz deficit in max turbo. Albeit the latter is an advantage Intel carries onto desktop platforms, the former isn't (and won't be with Alder Lake either).

Golden Cove will not clock higher than Rocket Lake. I shouldn't even have to say more than that. Rocket Lake clocks at 5.3GHz single-core and a max all-core clock of 4.7GHz. Golden Cove's expected to hit 5-5.1GHz ST. If you're wondering why rumours have been suggesting 25% IPC and 20% ST performance - now you know.

Onto DDR5, that's both a benefit and a demerit. DDR5 makes SPR a much more costly platform vs Milan. But yes, as a tradeoff you do get significantly (50% per memory channel) better memory bandwidth (SPR supports DDR5-4800).

However I don't see this being a major benefit for Alder Lake. Very few consumer workloads benefit from higher memory bandwidth vs memory latency, which is where DDR4 will continue to have an advantage for a while still. Especially in gaming, memory latency is king. Where memory bandwidth is especially useful is for iGPUs.

Now if you consider me responding to comments you've made regarding AMD's competitiveness in 2022 which you've happened to make in the Intel thread, what about that makes me a troll? I won't deny that I have a pro-AMD bias - I'd be lying if I said I didn't - but I still at least try to be as fair as I can be based off of the data we have.
 

uzzi38

Golden Member
Oct 16, 2019
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Willow Cove is 18%+ faster per clock over Skylake, yet TGL-H is only 19% faster over Comet Lake when compared at 45W TDP. The jump from 14nm to 10SF brought just enough efficiency to compensate for the larger cores, not enough to allow for even more performance through higher clocks.

View attachment 44305
Exactly, and that's in an extremely power limited scenario like a laptop. What's obviously going to happen in a fully unlimited one like a desktop?
 
Feb 17, 2020
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The issue with only looking at IPC is that you need to consider the IPC/Cdyn ratio, especially in thermally constrained environments like mobile and server.

With your average bog-standard architectural change, every 1% IPC will typically get around 1% Cdyn. Then you factor in the power savings from a node jump, and you cram a bunch more IPC into the same power envelope. Perfectly fine.

With a really good architectural jump like Zen 2 to Zen 3, which had 20% IPC for under 10% Cdyn increase (> 2-to-1 ratio), you can come out ahead even if you don't move nodes.

Meanwhile, Skylake to Sunny cove is around a 1% IPC to 2% Cdyn ratio iso-process. That's really bad.

Golden Cove promising 20% IPC is all well and good, but if that comes with a 40% increase in Cdyn, you end up losing performance because you'll need to throttle.
 

Cardyak

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Sep 12, 2018
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The issue with only looking at IPC is that you need to consider the IPC/Cdyn ratio, especially in thermally constrained environments like mobile and server.

With your average bog-standard architectural change, every 1% IPC will typically get around 1% Cdyn. Then you factor in the power savings from a node jump, and you cram a bunch more IPC into the same power envelope. Perfectly fine.

With a really good architectural jump like Zen 2 to Zen 3, which had 20% IPC for under 10% Cdyn increase (> 2-to-1 ratio), you can come out ahead even if you don't move nodes.

Meanwhile, Skylake to Sunny cove is around a 1% IPC to 2% Cdyn ratio iso-process. That's really bad.

Golden Cove promising 20% IPC is all well and good, but if that comes with a 40% increase in Cdyn, you end up losing performance because you'll need to throttle.
This is a very salient point, I was thinking of this not long ago. IPC is a useful metric for gauging performance (when taking into account clock speed of course), but in order to truly get a picture of the perf/watt you need to look at the ratio of transistors utilized in the design and TDP, and then cross reference that with your IPC gain.

I believe Intel did have a design ethos at one time which was something along the lines of: "For every 1% increase in power, a microarchitecture feature should deliver at least 2% IPC improvement." Not sure what happened to this approach but if Sunny/Willow Cove are anything to go by I think we can assume this philosophy was dropped a while ago.
 
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ondma

Platinum Member
Mar 18, 2018
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The issue with only looking at IPC is that you need to consider the IPC/Cdyn ratio, especially in thermally constrained environments like mobile and server.

With your average bog-standard architectural change, every 1% IPC will typically get around 1% Cdyn. Then you factor in the power savings from a node jump, and you cram a bunch more IPC into the same power envelope. Perfectly fine.

With a really good architectural jump like Zen 2 to Zen 3, which had 20% IPC for under 10% Cdyn increase (> 2-to-1 ratio), you can come out ahead even if you don't move nodes.

Meanwhile, Skylake to Sunny cove is around a 1% IPC to 2% Cdyn ratio iso-process. That's really bad.

Golden Cove promising 20% IPC is all well and good, but if that comes with a 40% increase in Cdyn, you end up losing performance because you'll need to throttle.
In order to "lose performance" with a 20% IPC increase, clockspeed would have show a greater than 20% decrease. Are you seriously trying to say Golden Cove will only clock slightly above 4ghz? I believe GC will also be on a further enhanced process so my estimation is that it will clock at least a high or maybe higher.

Edit: compared to other 10nm products, i.e. around 5 ghz.
 
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Feb 17, 2020
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In order to "lose performance" with a 20% IPC increase, clockspeed would have show a greater than 20% decrease. Are you seriously trying to say Golden Cove will only clock slightly above 4ghz? I believe GC will also be on a further enhanced process so my estimation is that it will clock at least a high or maybe higher.
Poor wording on my part, I should have clarified that you CAN end up losing performance.

I'm mainly referring to mobile/server workloads, which are Intel's (and AMD's) main money-movers. You could definitely have cores throttle by over 20%.
 

Exist50

Senior member
Aug 18, 2016
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Poor wording on my part, I should have clarified that you CAN end up losing performance.

I'm mainly referring to mobile/server workloads, which are Intel's (and AMD's) main money-movers. You could definitely have cores throttle by over 20%.
Keep in mind that clock scaling, all else equal, implies voltage scaling. For that reason, even a quite bad 1:2 IPC:Cdyn ratio will still provide power savings at the same performance level (assuming leakage isn't crazy). But yes, without process scaling to keep things in check, you end up with significantly higher power with both at max performance.
 
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Feb 17, 2020
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Keep in mind that clock scaling, all else equal, implies voltage scaling. For that reason, even a quite bad 1:2 IPC:Cdyn ratio will still provide power savings at the same performance level (assuming leakage isn't crazy). But yes, without process scaling to keep things in check, you end up with significantly higher power with both at max performance.
Yeah, I'm definitely oversimplifying. Leakage, area, and supply droop are huge factors as well.
 

coercitiv

Diamond Member
Jan 24, 2014
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I believe Intel did have a design ethos at one time which was something along the lines of: "For every 1% increase in power, a microarchitecture feature should deliver at least 2% IPC improvement." Not sure what happened to this approach but if Sunny/Willow Cove are anything to go by I think we can assume this philosophy was dropped a while ago.
I think this was related to the original goals of the Atom team. All their IPC jumps had to be met with a corresponding increase in (energy) efficiency as well, they couldn't rely on node efficiency jumps to carry them through.

Actually based on you mentioning this 2:1 ratio I was finally able to find a reference to this info:
Atom's architects, similar to those who worked on Nehalem, had the same 2:1 mandate: every new feature added to the processor's design had to deliver at least a 2% increase in performance for every 1% increase in power consumption.
 

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