Discussion Intel current and future Lakes & Rapids thread

[jpiniero]

Only 56?! The package footprint looks huge. I also thought that SPR will have two CPU dice per package. Seems a bit sad that Intel still won't get to 64 cores with that setup.

It's four. The client Golden Cove is probally going to be very large as it is, plus you have to add the second AVX-512 unit plus AMX and all the server fun stuff.

 

[Ajay]

It's four. The client Golden Cove is probally going to be very large as it is, plus you have to add the second AVX-512 unit plus AMX and all the server fun stuff.

Thanks. Forgot about the second AVX unit and AMX - going senile I guess. Intel is really doubling down on ML/DL.

 

[jpiniero]

https://twitter.com/x/status/1379802329382219777

Intel doing an Ice Lake Xeon D. Bigger one has up to 20 cores, the Smaller one has up to 8. Release isn't any time soon though, says sampling in Q3/Q4.

 

[DrMrLordX]

Not sure why would anyone want an early sample.

Facebook wanted Cooper Lake. I would assume they would want Ice Lake-SP for many of the same reasons. At least in sufficiently high core counts anyway.

It's four. The client Golden Cove is probally going to be very large as it is, plus you have to add the second AVX-512 unit plus AMX and all the server fun stuff.

Wait

AMX on Intel CPUs? What am I missing here?

 

[jpiniero]

AMX on Intel CPUs? What am I missing here?

The x86 Advanced Matrix Extension (AMX) Brings Matrix Operations; To Debut with Sapphire Rapids

Intel publishes details of its upcoming Advanced Matrix Extension (AMX), an x86 extension set to debut with Sapphire Rapids that introduces a new matrix register file and accompanying matrix operations.

fuse.wikichip.org

 

[DrMrLordX]

@jpiniero

Ah, thanks for the clarification. Nice of em to give it the same name as Apple's AMX.

 

[Exist50]

@jpiniero

Ah, thanks for the clarification. Nice of em to give it the same name as Apple's AMX.

I don't think Apple's publicly given their matrix extensions a name. People have been calling it AMX after Intel's.

 

[IntelUser2000]

Sapphire Rapids will close that gap considerably.

EDIT: According to rumors, SR will feature up to 56 golden cove cores.

According to rumors Sapphire Rapids might have up to 72 cores. It'll probably beat Milan, but Genoa with 5nm is supposed to be a big advancement. Considering AMD is planning a refresh of Zen 3 later this year, I guess the only positive is they'll potentially have few months of breathing room.

 

[2blzd]

I was just reading that SR maxed out at 56. 4 tiles of 15c with 1c disabled on each. How would they hit 72? 6 tiles with 12 cores?

 

[eek2121]

Only 56?! The package footprint looks huge. I also thought that SPR will have two CPU dice per package. Seems a bit sad that Intel still won't get to 64 cores with that setup. I suppose that I/O and the mem controller will be pretty large on those dice.

Golden Cove is considerably larger (and faster) than anything either Intel or AMD has out today. Intel is apparently still going to launch this year so they might have a leg up on AMD for a few months. We will see.

 

[eek2121]

According to rumors Sapphire Rapids might have up to 72 cores. It'll probably beat Milan, but Genoa with 5nm is supposed to be a big advancement. Considering AMD is planning a refresh of Zen 3 later this year, I guess the only positive is they'll potentially have few months of breathing room.

The biggest chip I've seen leaked is 56 cores. Genoa won't be out until next year unless AMD decides to surprise us.

Initial Sapphire Rapids chips are going into "super computers", same with Genoa.

 

[Exist50]

According to rumors Sapphire Rapids might have up to 72 cores.

Investigated. Rejected.

 

[ashFTW]

Investigated. Rejected.

Lets do some very ROUGH math: The 40 core ICL die is 628 mm2 (according to Wikichip). The delidded SPR “tile” has been estimated to be 370mm2, and (in one of SPR configurations) there are four of them for a total of 1480mm2. 1480/628 is approx 2.35. 40 x 2.35 is 94 cores!! Of course the SPR core is bigger than ICL, but perhaps that‘s balanced by the uncore size of SPR, which is most likely not 2.35 that of ICL given that SPR is rumored to still be 8 DDR5 channels.

If the leaks are to be believed, SPR has the potential to be competitive against the rumored 96 cores of Genoa.

Sapphire Rapids delidded

Quotes Quote Being a sample rather than a commercial product, the processor is marked as Intel Confidential and features the QVV5 sSpec, along with a 1.30 GHz frequency. The image was published by YuuKi_AnS, a known hardware leaker who sometimes has access to unreleased chips. We confirmed the CP...

linustechtips.com

Intel Launches 3rd Gen Ice Lake Xeon Scalable

Intel launches its 3rd Generation Xeon Scalable, formerly Ice Lake. Fabricated on the company's 10nm process, those server chips go up to 40 Sunny Cove cores and offer a 20% IPC improvement over the prior generation.

fuse.wikichip.org

 

[Exist50]

Lets do some very ROUGH math: The 40 core ICL die is 628 mm2 (according to Wikichip). The delidded SPR “tile” has been estimated to be 370mm2, and (in one of SPR configurations) there are four of them for a total of 1480mm2. 1480/628 is approx 2.35. 40 x 2.35 is 94 cores!! Of course the SPR core is bigger than ICL, but perhaps that‘s balanced by the uncore size of SPR, which is most likely not 2.35 that of ICL given that SPR is rumored to still be 8 DDR5 channels.

If the leaks are to be believed, SPR has the potential to match the rumored 96 cores of Genoa.

Sapphire Rapids delidded

Quotes Quote Being a sample rather than a commercial product, the processor is marked as Intel Confidential and features the QVV5 sSpec, along with a 1.30 GHz frequency. The image was published by YuuKi_AnS, a known hardware leaker who sometimes has access to unreleased chips. We confirmed the CP...

linustechtips.com

Intel Launches 3rd Gen Ice Lake Xeon Scalable

Intel launches its 3rd Generation Xeon Scalable, formerly Ice Lake. Fabricated on the company's 10nm process, those server chips go up to 40 Sunny Cove cores and offer a 20% IPC improvement over the prior generation.

fuse.wikichip.org

Your numbers/math are wrong. SPR is 60/56 cores, and will not come anywhere close to matching Genoa.

 

[ashFTW]

Your numbers/math are wrong. SPR is 60/56 cores, and will not come anywhere close to matching Genoa.

which number is wrong? 628, or 1480? Did you look at the links? My math is just diving two numbers.

 

[Exist50]

which number is wrong? 628, or 1480? Did you look at the links? My math is just diving two numbers.

Core growth, IO growth, D2D overhead. You cannot just take ICX and scale up.

 

[ashFTW]

Core growth, IO growth, D2D overhead. You cannot just take ICX and scale up.

The 2.35 scale should easily account for IO growth and D2D EMIB overhead. Even if the SPR core is 20% bigger, that‘s still 94x0.8 =75 cores.

 

[uzzi38]

The 2.35 scale should easily account for IO growth and D2D EMIB overhead. Even if the SPR core is 20% bigger, that‘s still 94x0.8 =75 cores.

That 2.35x scale you "calculated" is just SPR's die area divided by ICL-SP's die area. It doesn't account for SPR having vastly more die area per tile dedicated towards I/O.

Phrasing it differently, the ratio of die area dedicated to uncore to vs to cores will be rising with SPR. You can't just scale up ICL-SP to estimate the number of cores on die.

 

[ashFTW]

That 2.35x scale you "calculated" is just SPR's die area divided by ICL-SP's die area. It doesn't account for SPR having vastly more die area per tile dedicated towards I/O.

Phrasing it differently, the ratio of die area dedicated to uncore to vs to cores will be rising with SPR. You can't just scale up ICL-SP to estimate the number of cores on die.

I gave 2.35 times ICL uncore area to SPR uncore. Do you think it’s going to be more?? It has same number of memory channels; i know it’s DDR5 instead of DDR4. SPR may have more PCIe 5 lanes as well, but 235% is quite generous.

Of course one can‘t just scale up. That’s why i said ROUGH calculation, to show 56/60 is a gross underestimate. 1480mm2 is a LOT of silicon!

I don’t have a horse in the race. My next workstation will be 64+ core Genoa or SPR, whichever I can get at a reasonable price.

 

[uzzi38]

Intel Sapphire Rapids to feature up to 56 cores, 350W TDP and 64GB of HBM2 memory - VideoCardz.com

Intel 4th Gen Xeon Scalable (Sapphire Rapids) More cores, more PCIe lanes, and support for next-gen interfaces. We received an anonymous tip with a slide featuring Intel’s future Xeon platform specifications. The slide is dated, as it still lists the Ice Lake server as a 2020 product, however it...

videocardz.com

There you go, 56 cores. Any other questions?

 

[IntelUser2000]

I gave 2.35 times ICL uncore area to SPR uncore. Do you think it’s going to be more?? It has same number of memory channels; i know it’s DDR5 instead of DDR4. SPR may have more PCIe 5 lanes as well, but 235% is quite generous.

I doubt cores are only 20% larger.

Genoa may be coming 6-9 months later, but 30% higher perf/clock in addition to 50% extra cores and AVX-512. AMD is probably aiming for 2x gain over Milan.

Since Milan is not a big upgrade over Rome, it makes sense.

 

[JoeRambo]

There you go, 56 cores. Any other questions?

Still, how many times ICL-SP core counts have changed? If we were to believe rumours, it was 36 for quite some time, while actual die has 42 cores?
The core count per chip is of utmost importance, cause it decides the size of NUMA domain and maximum L3 cache accessible to single core.

AMD is most likely going to 12C chiplets and 96C to combat ARM monsters of 2022, so Intel having 14C chiplets would be dissapointing.

 

[uzzi38]

Still, how many times ICL-SP core counts have changed? If we were to believe rumours, it was 36 for quite some time, while actual die has 42 cores?
The core count per chip is of utmost importance, cause it decides the size of NUMA domain and maximum L3 cache accessible to single core.

AMD is most likely going to 12C chiplets and 96C to combat ARM monsters of 2022, so Intel having 14C chiplets would be dissapointing.

I don't think AMD are increasing the numbers of cores per chiplet instead of just increasing the number of chiplets.

SPR won't be too bad given it'll probably beat Milan, but yeah, it's not going to have a fun time vs Genoa.

 

[IntelUser2000]

Of course one can‘t just scale up. That’s why i said ROUGH calculation, to show 56/60 is a gross underestimate. 1480mm2 is a LOT of silicon!

The I/O takes up a greater portion on the smaller core dies.

For example ICX-SP LCC with 16 cores is at 370mm2 as well. The HCC with 28 cores is at 505mm2. The 40 core version is little over 600mm2.

 

[RTX]

Being fabbed on 10SF, which should be comparable to TSMC 7nm in density and efficiency, I think the Icelake Xeon review makes it pretty clear that Intel's newest cores are simply less efficient than current Zen. Tigerlake cores wouldn't change the equation much there.

https://twitter.com/x/status/1379462717833146368

https://twitter.com/x/status/1379453925947019271

Ian says they're 10nm+