Discussion Intel current and future Lakes & Rapids thread

[Hulk]

Price:

Intel 11th Gen Core "Rocket Lake" series official specifications and pricing - VideoCardz.com

Intel Core i9-11900K to cost 539 USD We have the final specification and pricing for the upcoming 11th Gen Core series. The flagship 8-core i9-11900K SKU will retail at 539 USD (pricing per 1000 units), an increase of 51 USD per CPU compared to Core i9-10900K. This CPU will boost up to 5.3 GHz...

videocardz.com

some guys start selling 11700/11700f slightly cheaper than 5600x in my country. IMO price/perf ratio is very good (*just for cpu. now all we need is a beefy mobo which might not be cheap*)

5800X down to $429 at MC.

 

[Hulk]

Rocket Lake - One die, 19 models based on yields. Sorted by price to "see" how Rocket Lake is yielding for Intel, or at least based in how they are pricing. It's nice that they designate the models without a GPU with "F" so I can remember that has "failed GPU test." T models are most likely a little more rare on the wafer as they are low leakage/low power parts.

Same tier number means same CPU clocks.

	Model	1T max	nt Max	Price
1	11900K	5300	4700	$539	Tier 1
2	11900KF	5300	4700	$513	Tier 1g - Broken GPU
3	11900	5200	4600	$439	Tier 2
4	11900T	4900	3700	$439	Low leakage/Low clocking
5	11900F	5200	4600	$433	Tier 2g - Broken GPU
6	11700K	5000	4600	$399	Tier 3
7	11700KF	5000	4600	$374	Tier 3g - Broken GPU
8	11700	4900	4400	$323	Tier 4
9	11700T	4600	3600	$323	Low leakage/Low clocking
10	11700F	4900	4400	$298	Tier 4g - Broken GPU
11	i5-11600K	4900	4600	$262	Tier 5 - Failed cores
12	i5-11600KF	4900	4600	$237	Tier 5g - Failed cores and failed GPU
13	i5-11600	4800	4300	$213	Tier 6 - Failed cores
14	i5-11600T	4100	3500	$213	Low leakage/Low clocking/Failed cores
15	i5-11500	4600	4200	$192	Tier 7 - Failed cores
16	i5-11500T	3900	3400	$192	Low leakage/Low clocking/Failed cores
17	i5-11400	4400	4200	$182	Tier 8 - Failed cores
18	i5-11400T	3700	3300	$182	Low leakage/Low clocking/Failed cores
19	i5-11400F	4400	4200	$157	Tier 8g - Failed cores and failed GPU

 

[cortexa99]

5800X down to $429 at MC.

yeah I also notice 11700k price(520$) is absurdly high at MC, from 11700k review thread. Wonder what's going on, too different from Intel's official price.

alright newegg has good price which are in line with official
https://www.reddit.com/r/intel/comments/m6b6fa

 

[Zucker2k]

RKL-S Presentation Slides:

 

[Zucker2k]

Continuation....

 

[Zucker2k]

Continuation.....

 

[Zucker2k]

Continuation.....









Source: https://www.hardwareluxx.de/index.php/galerie/komponenten/prozessoren/intel-rocket-lake-s-deepdive.html

 

[Racan]

Why are they posing in front of a ballistic missile? lol

 

[Thala]

You are brushing aside the vast differences in upcoming CPUs as if past ARM chips had to cover every possible situation (such as mix of AVX capabilities on different cores on the same chip). You also ignored that Microsoft later decided to toss some of that scheduling out and just go with reserved core and reserved threads for the operating system (also on my list) for the Xbox Series X (item #1 on my list).

You do confuse a few things. First of all, the cores will not be heterogenous with respect to their compute/instruction set capabilities. Second, the fact that Microsoft decided to fix the affinity of some threads on XBox has nothing to do with the heterogenous scheduling algorithm discussed in this context.

 

[Thala]

Good info. Thanks. When a core moves "up" if saturated I assume that means up in compute priority?

No. These are orthogonal concepts. A thread might have high priority but low compute requirements and vice versa. That having said, the scheduler still schedules threads, which have higher priority first.

As far as having impact on the scheduling programmatically, you have the option of setting the priority, the affinity (this was always possible even before big.LITTLE) and with the new heterogenous scheduler, you can give scheduling hints using the SetThreadInformation API.

 

[dullard]

First of all, the cores will not be heterogenous with respect to their compute/instruction set capabilities.

If true, then that is new news. All along the rumors were that the big and little cores have different instruction sets and thus threads could not just be scheduled from one to the other using simpler ARM-like scheduling. Example link: https://www.techpowerup.com/269835/intel-alder-lake-cpu-core-segmentation-sketched

The big "Golden Cove" core supports certain AVX-512 instructions, besides TSX-NI (tensor operations, matrix multiplication), and FP16 (half precision floating point). The smaller "Gracemont" core lacks these instruction sets.

The rumors were that new scheduling algorithms need to be made, or just simple either/or scheduling like I posted need to be performed.

Second, the fact that Microsoft decided to fix the affinity of some threads on XBox has nothing to do with the heterogenous scheduling algorithm discussed in this context.

I bring that up since you said scheduling was a done, solved issue. Then years after coming up with that One Kernel, Microsoft itself decided it needed something better. Thus, it is not completed work.

 

[Thala]

If true, then that is new news. All along the rumors were that the big and little cores have different instruction sets and thus threads could not just be scheduled from one to the other using simpler ARM-like scheduling. Example link: https://www.techpowerup.com/269835/intel-alder-lake-cpu-core-segmentation-sketched

The rumors were that new scheduling algorithms need to be made, or just simple either/or scheduling like I posted need to be performed.

Actually thats not particularly new information. Just look at Lakefield. The rest is just rumors.

Besides even if this would be the case, it would not change the scheduler at all - as it would have the same effect as an affinity mask - which is already supported. The problem with such an approach lies elsewhere - at thread creation time, it is not known to the OS, if the thread will eventually use AVX instructions. There have been few proposals in the research community - none are really satisfying for a general purpose OS.
A related problem is, how the application queries the core capabilities. It is typically using the CPUID instruction. When the application runs on the less featured core, when using CPUID, i hope you can figure what happens...

I bring that up since you said scheduling was a done, solved issue. Then years after coming up with that One Kernel, Microsoft itself decided it needed something better. Thus, it is not completed work.

You have to understand, that this feature (mapping certain threads to a subset of available cores) is supported since literally forever - and is not new feature with respect to the heterogenous scheduler discussed in this context.

 

[uzzi38]

You do confuse a few things. First of all, the cores will not be heterogenous with respect to their compute/instruction set capabilities. Second, the fact that Microsoft decided to fix the affinity of some threads on XBox has nothing to do with the heterogenous scheduling algorithm discussed in this context.

With Alder Lake the cores themselves won't have the same ISA support, but only the lowest common denominator of instructions will be enabled when the little cores are active. So for all intents and purposes, Windows will see the big and little cores as having the same ISA support.

 

[Thala]

So for all intents and purposes, Windows will see the big and little cores as having the same ISA support.

Thats precisely my point And this also applies to the applications, when running on such a machine (see my CPUID argument above)

 

[dullard]

With Alder Lake the cores themselves won't have the same ISA support, but only the lowest common denominator of instructions will be enabled when the little cores are active. So for all intents and purposes, Windows will see the big and little cores as having the same ISA support.

That is what I am getting at, there is a new problem to solve: how to use them with different ISA support. This is not the same old problem. It could be treated as the same like Thala describes. But, there is a new opportunity now.

 

[jpiniero]

That is what I am getting at, there is a new problem to solve: how to use them with different ISA support. This is not the same old problem. It could be treated as the same like Thala describes. But, there is a new opportunity now.

Windows barely works as it is. I doubt you will ever see cross-ISA support enabled on a client machine. My guess is that the next Small Core will support AVX-512.

 

[Thala]

Windows barely works as it is. I doubt you will ever see cross-ISA support enabled on a client machine. My guess is that the next Small Core will support AVX-512.

Optionally it is disabled for the big cores, just like in Lakefield. I currently do not see AVX-512 being implemented in Gracemont, mainly because its SW support is totally niche.
And to be honest, i do not see the point of a desktop CPU supporting big.LITTLE at all in general.

 

[jpiniero]

Optionally it is disabled for the big cores, just like in Lakefield.

It's not optional. You have the small cores enabled, AVX-512 won't be reported as available and will stay off.

I currently do not see AVX-512 being implemented in Gracemont, mainly because its SW support is totally niche.

Not Gracemont, Nextmont. You're talking about the 23-24 products so it's likely either on Intel 7 nm or TSMC at that point. Raptor Lake is the 22-23 product and while we don't know what Big Core it has, it's almost certainly Gracemont as it's Small Core.

And to be honest, i do not see the point of a desktop CPU supporting big.LITTLE at all in general.

Went over this already. Intel's only willing to do "10" max on the Ring, and 4 Small cores are going to beat 1 Big Core in most MT workloads. Plus Intel has enough low power desktop customers to make it worthwhile, not to mention the S BGA laptops and AIOs.

Until Intel abandons the Ring on mainstream client, this is how it's going to be.

 

[HurleyBird]

AVX 512 on the small cores will make them... not small anymore.

An interesting implementation would be to take a page out of Bulldozer's book, so that vector resources are shared between multiple cores. So, maybe you have quad core clusters of small cores that each have a single 512-bit vector unit which can then be partitioned into 2x 256-bit, 4x 128-bit, or 1x 256-bit + 2x 128-bit depending on need.

 

[Thala]

It's not optional. You have the small cores enabled, AVX-512 won't be reported as available and will stay off.

I was under the impression we were talking Alderlake. But it does not really matter for the sake of the discussion about heterogenous schedulers. My point was that the ISA features will be the same among all cores in any case - be it with or without AVX-512.
Besides this is the main reasons Cortex A78/X1 is still largely ARMv8.2A compliant, despite the specification moved up to ARMv8.6A. This is also the baseline for Windows.

Not Gracemont, Nextmont. You're talking about the 23-24 products so it's likely either on Intel 7 nm or TSMC at that point. Raptor Lake is the 22-23 product and while we don't know what Big Core it has, it's almost certainly Gracemont as it's Small Core.

See above.

 

[jpiniero]

I was under the impression we were talking Alderlake.

I am. I could see AVX-512 being allowed with both Big and Small cores enabled but it would only be in a controlled environment. Like Linux embedded.

 

[DrMrLordX]

I agree that there will likely be a latency penalty, but the original post claimed they were on separate dies which is obviously false.

I honestly thought Intel would trot out EMIB for Alder Lake! It's surprising that they didn't.

AVX 512 on the small cores will make them... not small anymore.

Just because it can support AVX512 instructions doesn't mean it absolutely needs the execution resources to run at full speed executing said instructions.

 

[lobz]

Well, the ball is in AMD's court, as they say. If they wanna keep anything from their really hard earned current mindshare, they have to massively improve supply AND however painful that may be, bring Zen 3 prices back to where they would have been, had Intel launched RKL in time (before or right around Zen 3 launch).

Chances are of course that none of these 2 can and will happen.

 

[lobz]

yeah I also notice 11700k price(520$) is absurdly high at MC, from 11700k review thread. Wonder what's going on, too different from Intel's official price.

alright newegg has good price which are in line with official
https://www.reddit.com/r/intel/comments/m6b6fa

I'd say, a $429 5800X is still not convincing against a $399 11700K in itself - we'll have to wait and see how proper mobo prices compare.

 

[Hulk]

I'd say, a $429 5800X is still not convincing against a $399 11700K in itself - we'll have to wait and see how proper mobo prices compare.

Wow just goes to show how different perspectives can be. I was thinking just the opposite. AMD looks to equal or beat Intel's best with their #3 (5800X). From my point of view Intel needs to move the 11900K price to $399 and drop all 18 of the other binned Rocket parts below that price. I think AMD is more than competitive right now without lifting a finger.