Discussion Intel current and future Lakes & Rapids thread

[DrMrLordX]

What are the odds that we see the 10C 10th gen parts dry up really quickly?

Depends on how many Rocket Lake-S parts they push onto the market. Rocket Lake-S only covers a small portion of Intel's total product profile as well. So yeah we may see products like the 10900k become scarce, but lower-end stuff will likely still be widely-available.

 

[AMDK11]

The irony is that it was in fact C2D core with IMC bolted on. So it was PPRO derivative with IMC bolted on, QPI for interconnect and HT enabled. Uncore was different, but just like Sunny Cove to Willow Cove is "same core" with different cache architecture, it was same with C2D versus Nehalem. Of course what was truly revolutionary for customre was $266 triple channel quad that ran 3.8Ghz+
Biggest leap since Pentium PRO happened with Sandy Bridge, now that is core architecture that Intel is using basically to this day with some ports added and buffers widened.

I do not agree with that. Nehalem, while a direct successor to Conroe, is actually a redesigned and basically new x86 core with new features. Conroe and Penryn is the same as SunnyCove and WillowCove, as is Nehalem and Westmere, except WillowCove makes far-reaching changes to the cache subsystem. Penryn introduced a larger L2 cache compared to Conroe + additional SSE4.1 and 4.2 instructions. Nehalem was a new x86 core with a dozen or so percent increase in IPC for ST and quite large for SMT.

1. Conroe - new x86 core at 65nm
2. Penryn - Conroe with new SSE4 instructions, larger L2 in new 45nm manufacturing process

1. Nehalem - new x86 core at 45nm
2. Westmere - Nehalem with new AES instructions in a new 32nm process

1. SandyBridge - new x86 core at 32nm
2. IvyBridge - SandyBridge with bug fixes and new random number generator instructions at 22nm

1. Haswell - new x86 core at 22nm
2. Broadwell - Haswell with fixes and new instructions in 14nm

1.Skylake - new x86 core at 14nm
2.Cannonlake - Skylake with fixes and new instructions in 10nm (that was the original assumption)

1.SunnyCove - new x86 core at 10nm
2. WillowCove - SunnyCove with redesigned cache subsystem in 10nmSF

1.GoldenCove - new x86 core in E10nmSF etc.

 

[majord]

The gaming performance in those reviews better be way off the mark for final silicon, or it will be an embarrassment.

Other performance metrics seem to check out with expectations so must be something memory or cache related.

 

[Zucker2k]

The gaming performance in those reviews better be way off the mark for final silicon, or it will be an embarrassment.

Other performance metrics seem to check out with expectations so must be something memory or cache related.

Must be the decoupled NB. I think Intel has locked that in the QS chips to mask final performance.

 

[dullard]

What are the odds that we see the 10C 10th gen parts dry up really quickly?

OEMs tend to sell older generation chips for quite a while. Dell still sells the 8th and 9th generation chips. Example:

OptiPlex XE3 | Dell USA

Enhanced performance, expandable industrial-grade PC featuring high heat tolerance and exceptional manageability.

www.dell.com

I don't think the 10th generation will dry up too quickly, unless the chip shortage kicks up into an even higher gear. A lot of that demand has been in the low end - people buying the cheapest CPU products for work from home or for mining. Combine that with Intel making more profit on the high-end and the low-end has been out of stock much more.

 

[lobz]

Must be the decoupled NB. I think Intel has locked that in the QS chips to mask final performance.

I enjoy a good comedy before going to sleep.

 

[uzzi38]

I enjoy a good comedy before going to sleep.

It depends on the review, but he's not wrong. It currently works the same way as Zen 2/Zen 3 - memory above DDR4-3600 will effectively enter 1:2 mode.

However, it's a toggleable setting in the BIOS. I don't think these reviewers are setting the AMD systems to 1:1 while leaving their RKL systems at 1:2.

EDIT: I just realised that the review I think most related to this is the following one:

They're using DDR4-4000cl17 to test here. The 5700G and 5800X both have PBO enabled (no CO), the 11900K has been overclocked (per core overclocking to be specific). They scored 719.6 in the CPU-z 1T test so it's safe to assume their chip has one core clocking in at 5.4GHz - give or take 100MHz.

I say that because in their original review of the chip at stock it scored 693pts 1T.

Gaming performance here is basically on oar with the 5800X, with the 11900K taking a strong lead in productivity, surprisingly enough. That being said, either there is firmware bugs or their overclock is unstable, because they also commented on repeated crashing and BSODs.

 

[blckgrffn]

OEMs tend to sell older generation chips for quite a while. Dell still sells the 8th and 9th generation chips. Example:

OptiPlex XE3 | Dell USA

Enhanced performance, expandable industrial-grade PC featuring high heat tolerance and exceptional manageability.

www.dell.com

I don't think the 10th generation will dry up too quickly, unless the chip shortage kicks up into an even higher gear. A lot of that demand has been in the low end - people buying the cheapest CPU products for work from home or for mining. Combine that with Intel making more profit on the high-end and the low-end has been out of stock much more.

Ah, I meant the 10C parts specifically (and perhaps the 8 core parts as well). With the new RKL parts available it seems like unless they have a higher margin they should disappear so that they can have better control over their product line in terms of forecasting demand. It wouldn't be much fun to be the guys in charge of hitting numbers when they have such a mixed channel and messaging.

If they have built up a huge supply of 10C parts (and hence the price cuts) due to lower than forecasted sales despite all that's happened on the supply side that's on those spreadsheet warriors to straighten out without damaging the brand value of i7/i9. Good luck to them.

For example, it seems like the smaller die 10th Gen Parts (the six core and below, right?) would remain while the 11th gen parts would replace the rest in most channels, especially retail.

I mean, you can still buy 9th gen Core i9s but they are the pinnacle of a socket and so can demand margin. The 10th gen parts aren't supposed to be better than the 11th gen stuff, I would wager.

Finally, I am sure that Dell is contractually bound to supply some "common platform/stable platform" type PC's for long periods of time, like 3-5 years for some corporate customers. That can keep them hanging them around for a long time too, especially in business oriented lines.

 

[ondma]

It seems like Intel must have some strategy for managing this, on behalf of their OEMs as well.

What are the odds that we see the 10C 10th gen parts dry up really quickly?

The 10700 really seems like the integrator darling right now anyway.

FWIW, I am hoping that 10700k is ~$350 as well, but that still doesn't help the average consumer much. I mean, you are asking them to choose between an 8 core or a 10 core product with very similar clockspeeds, no coolers, etc. at the same price? I can't blame anyone who shrugs and takes the higher core count.

I would take an 8 core with 10-15% higher IPC and similar or faster clocks any day of the week. It will be faster in anything but the most heavily threaded workloads, and within 10 to 15 percent in multithreaded. The problem for Intel, is that AMD has finally caught up in single thread and is ahead in providing lots of cores. Their problem has been the high price and poor availability of the 5xxx series, but that seems to be improving now.

 

[Hulk]

I do not agree with that. Nehalem, while a direct successor to Conroe, is actually a redesigned and basically new x86 core with new features. Conroe and Penryn is the same as SunnyCove and WillowCove, as is Nehalem and Westmere, except WillowCove makes far-reaching changes to the cache subsystem. Penryn introduced a larger L2 cache compared to Conroe + additional SSE4.1 and 4.2 instructions. Nehalem was a new x86 core with a dozen or so percent increase in IPC for ST and quite large for SMT.

1. Conroe - new x86 core at 65nm
2. Penryn - Conroe with new SSE4 instructions, larger L2 in new 45nm manufacturing process

1. Nehalem - new x86 core at 45nm
2. Westmere - Nehalem with new AES instructions in a new 32nm process

1. SandyBridge - new x86 core at 32nm
2. IvyBridge - SandyBridge with bug fixes and new random number generator instructions at 22nm

1. Haswell - new x86 core at 22nm
2. Broadwell - Haswell with fixes and new instructions in 14nm

1.Skylake - new x86 core at 14nm
2.Cannonlake - Skylake with fixes and new instructions in 10nm (that was the original assumption)

1.SunnyCove - new x86 core at 10nm
2. WillowCove - SunnyCove with redesigned cache subsystem in 10nmSF

1.GoldenCove - new x86 core in E10nmSF etc.

This is fun and it is also dangerous territory in a forum because it is so debatable.
But we are all friends here so here's my take on Intel architectural generations.

I personally think Alder Lake will be Intel's 14th desktop microprocessor architecture.
Let's review.

I hope I don't regret this!

1. 1978 - 8086 - I'm calling this the beginning of x86
2. 80286 - Doubling of IPC, non-multiplexed buses, better prefetch, buffering, jumps
3. 80386DX - 3 stage pipe, fully 32 bit, real/protected/virtual modes
4. 486DX - Double IPC, on chip unified cache, on chip FPU, enhanced bus interface
5. Pentium (P5) - 40% better IPC over 486 due mainly to superscaler design, better FP, separate data/instruction cache. I'm including everything from P5 to Tillamook in this generation.
6. P6 - Speculative execution, OoO "dynamic" execution, Superpipeling 5 to 14 stages. I'm calling P6 architecture everything from the Pentium Pro to Core (Yonah).
7. Pentium 4 - Netburst, yeah, new architecture that didn't work out so well
8. Conroe/Penryn - Double IPC, Better OoO prediction, wider engine, smart cache, 128bit SSE
9. Nehalem/Westmere - Macro-ops fusion better, loop stream detection, pipe goes to 16, new cache, better branch prediction, return of HT, on die memory controller (finally), turbo clocks
10. Sandy/Ivy Bridge - New branch predictor, physical register file, better turbo, ring bus, micro-op cache, prefetcher improvement, fp/int improvement, MOV operation improvement
11. Has/Broadwell - Wider execution engine, larger OoO buffer, better branch predictor, better/more in-flight loads, double cache bandwidth, better memory controller, 50% larger TLB
12. Skylake - Wider front end, larger reorder buffer, more integer registers/in-flight stores, scheduler entries. This generation includes everything from Skylake to Comet Lake.
13. Ice/Tiger/Rocket Lake - 50% larger L1, double L2, larger reorder buffer, more in-flights loads/stores, better scheduler, 8 to 10 execution ports (wider back end), larger micro-op cache
14. Alder Lake - Cool big/little cores that do stuff faster with less electron movement... hopefully

 

[majord]

This is fun and it is also dangerous territory in a forum because it is so debatable.
But we are all friends here so here's my take on Intel architectural generations.

I personally think Alder Lake will be Intel's 14th desktop microprocessor architecture.
Let's review.

I hope I don't regret this!

1. 1978 - 8086 - I'm calling this the beginning of x86
2. 80286 - Doubling of IPC, non-multiplexed buses, better prefetch, buffering, jumps
3. 80386DX - 3 stage pipe, fully 32 bit, real/protected/virtual modes
4. 486DX - Double IPC, on chip unified cache, on chip FPU, enhanced bus interface
5. Pentium (P5) - 40% better IPC over 486 due mainly to superscaler design, better FP, separate data/instruction cache. I'm including everything from P5 to Tillamook in this generation.
6. P6 - Speculative execution, OoO "dynamic" execution, Superpipeling 5 to 14 stages. I'm calling P6 architecture everything from the Pentium Pro to Core (Yonah).
7. Pentium 4 - Netburst, yeah, new architecture that didn't work out so well
8. Conroe/Penryn - Double IPC, Better OoO prediction, wider engine, smart cache, 128bit SSE
9. Nehalem/Westmere - Macro-ops fusion better, loop stream detection, pipe goes to 16, new cache, better branch prediction, return of HT, on die memory controller (finally), turbo clocks
10. Sandy/Ivy Bridge - New branch predictor, physical register file, better turbo, ring bus, micro-op cache, prefetcher improvement, fp/int improvement, MOV operation improvement
11. Has/Broadwell - Wider execution engine, larger OoO buffer, better branch predictor, better/more in-flight loads, double cache bandwidth, better memory controller, 50% larger TLB
12. Skylake - Wider front end, larger reorder buffer, more integer registers/in-flight stores, scheduler entries. This generation includes everything from Skylake to Comet Lake.
13. Ice/Tiger/Rocket Lake - 50% larger L1, double L2, larger reorder buffer, more in-flights loads/stores, better scheduler, 8 to 10 execution ports (wider back end), larger micro-op cache
14. Alder Lake - Cool big/little cores that do stuff faster with less electron movement... hopefully

As difficult as it is to find a breaking point, there's no way P6 can span to Yonah.

 

[Ajay]

As difficult as it is to find a breaking point, there's no way P6 can span to Yonah.

Well, the P6 changed everything. Moving to a RISC like core with a hardware JIT translator made all the difference to x86's survival.

 

[Hulk]

As difficult as it is to find a breaking point, there's no way P6 can span to Yonah.

That was really well said. You are probably right, that is a HUGE leap I made there! I think it may be best divided as P6 being Pentium Pro, Pentium II, Pentium III.

Then perhaps Core?
Pentium-M - Banias, Dothan, Yonah
Big changes internally here with pipe going 6 to 10 stages, micro-ops fusion, dedicated stack register management, SSE2/3 instructions

That would actually bridge nicely into the Core 2 generation so we'd have as follows.
Yes I think this make more sense. Pentium to Pentium Pro/PII/PIII to Core (Pentium-M) to Core2Duo (Conroe).

What do you think? So ADL would be Intel's 15th architecture.

1. 1978 - 8086 - I'm calling this the beginning of x86

2. 1982 - 80286 - Doubling of IPC, non-multiplexed buses, better prefetch, buffering, jumps

3. 1985 - 80386DX - 3 stage pipe, fully 32 bit, real/protected/virtual modes

4. 1989 - 486DX - Double IPC, on chip unified cache, on chip FPU, enhanced bus interface

5. 1993 - Pentium (P5) - 40% better IPC over 486 due mainly to superscaler design, better FP, separate data/instruction cache. I'm including everything from P5 to Tillamook in this generation.

6. 1995 - P6 (Pentium Pro, PII, PIII) - Speculative execution, OoO "dynamic" execution, Superpipeling 5 to 14 stages.

7. 2000 - Pentium 4 - Netburst, yeah, new architecture that didn't work out so well

8. 2003 - Core (Pentium M - Banias, Dothan, Yonah) - Pipeline going 6 to 10 stages, micro-ops fusion, dedicated stack register management, SSE2/3 instructions

9. 2006 - Core 2 (Conroe/Penryn) - Double IPC, Better OoO prediction, wider engine, smart cache, 128bit SSE

10. 2008 - Nehalem/Westmere - Macro-ops fusion better, loop stream detection, pipe goes to 16, new cache, better branch prediction, return of HT, on die memory controller (finally), turbo clocks

11. 2011 - Sandy/Ivy Bridge - New branch predictor, physical register file, better turbo, ring bus, micro-op cache, prefetcher improvement, fp/int improvement, MOV operation improvement

12. 2013 - Haswell/Broadwell - Wider execution engine, larger OoO buffer, better branch predictor, better/more in-flight loads, double cache bandwidth, better memory controller, 50% larger TLB

13. 2015 - Skylake(Sky/Kaby/KabyR/Coffee/Whiskey/Amber/Cannon/CoffeeR/Comet) - Wider front end, larger reorder buffer, more integer registers/in-flight stores, scheduler entries.

14. 2019 - Sunny Cove (Ice/Tiger/Rocket Lake) - 50% larger L1, double L2, larger reorder buffer, more in-flights loads/stores, better scheduler, 8 to 10 execution ports (wider back end), larger micro-op cache

15. 2021? - Alder Lake (Golden Cove/Gracemont) - Cool big/little cores that do stuff faster with less electron movement... hopefully

 

[mikk]

I agree totally. I'm just saying he shouldn't be so hyperbolic in his statements.

"Biggest launch since Conroe" "Uh, actually 21% improvement, beating the second best launch by 0.235% because we were able to more heavily weight the AVX enabled benches"

As John Lennon said, "Just gimme some truth man."

If you can't comment on unreleased products then don't make vague statements that imply massive improvements.

From where did you get 21%??? Also keep in mind this isn't only about IPC improvements, as I said the change to a hybrid design itself is a big change for Intels Core lineup, actually he said biggest architecture movement, don't you agree with this? He didn't say biggest launch, he said biggest architecture movement. You should be more specific with your answers. Alder Lake combines two fresh new microarchitectures and also brings support of DDR5 and PCIe5. Furthermore your "heavily weight AVX enabled benches" whining does't make real sense either because ADL Hybrid only supports AVX2 which is quite old by now, so in fact there can be a disadvantage to Sunny/Willow/Cypress which could make use of AVX512 in heavily weighted AVX benchmarks.

 

[Hulk]

From where did you get 21%??? Also keep in mind this isn't only about IPC improvements, as I said the change to a hybrid design itself is a big change for Intels Core lineup, actually he said biggest architecture movement, don't you agree with this? He didn't say biggest launch, he said biggest architecture movement. You should be more specific with your answers. Alder Lake combines two fresh new microarchitectures and also brings support of DDR5 and PCIe5. Furthermore your "heavily weight AVX enabled benches" whining does't make real sense either because ADL Hybrid only supports AVX2 which is quite old by now, so in fact there can be a disadvantage to Sunny/Willow/Cypress which could make use of AVX512 in heavily weighted AVX benchmarks.

It was sarcasm.

I was modeling how his statement could be technically true but the resulting product underwhelming. He is comparing the launch to Core so I'm expecting big things. That's all.

 

[jpiniero]

Intel to launch three 8-core 11th Gen Core 'Tiger Lake-H' series CPUs? - VideoCardz.com

Intel Tiger Lake-H from 6 to 8 cores. Tiger Lake CPUs with more than 4 cores are just around the corner. The first Tiger Lake-based processors for high-end gaming laptops have been introduced at CES 2021. Only this month’s first laptops with such CPUs have started to appear in stores...

videocardz.com

Intel has apparently decided to go back to the core counts comparable to Comet Lake with Tiger Lake H45 - there are two i9 and one i7 8 core model and a 6 core i5 one.

 

[JoeRambo]

I do not agree with that. Nehalem, while a direct successor to Conroe, is actually a redesigned and basically new x86 core with new features. Conroe and Penryn is the same as SunnyCove and WillowCove, as is Nehalem and Westmere, except WillowCove makes far-reaching changes to the cache subsystem. Penryn introduced a larger L2 cache compared to Conroe + additional SSE4.1 and 4.2 instructions. Nehalem was a new x86 core with a dozen or so percent increase in IPC for ST and quite large for SMT.

Actually not at all, it was C2D core with HT enabled and L2 and L3 changed. You don't have to take my word for it, compare C2D and Nehalem in contemporary sources like RWT:

Frontend:
Inside Nehalem: Intel's Future Processor and System (realworldtech.com)
OoO and ports
Inside Nehalem: Intel's Future Processor and System (realworldtech.com)

You can easily find similar stuff about Sandy Bridge and see what a different from C2D cores should look like.

 

[Carfax83]

Furthermore your "heavily weight AVX enabled benches" whining does't make real sense either because ADL Hybrid only supports AVX2 which is quite old by now, so in fact there can be a disadvantage to Sunny/Willow/Cypress which could make use of AVX512 in heavily weighted AVX benchmarks.

Wait a sec, so the big cores don't even support AVX-512? I thought that ALD would still support AVX-512, but it would be disabled when the little cores were engaged; which you could disable.

This seems like a massive step back if true. Intel has been on this pathway for several years now and just brought AVX-512 into the mainstream with Tiger Lake, but now their highest performance desktop core and the successor to Skylake won't have AVX-512?

 

[jpiniero]

Wait a sec, so the big cores don't even support AVX-512? I thought that ALD would still support AVX-512, but it would be disabled when the little cores were engaged; which you could disable.

I think most won't bother turning off hybrid mode.

 

[blckgrffn]

I think most won't bother turning off hybrid mode.

That would be my take as well. And if most enthusiasts disable the small cores permanently for whatever reason that’s going to call the strategy further into question.

 

[Carfax83]

I think most won't bother turning off hybrid mode.

Likely not, but it was still done haphazardly imo. Ice Lake and Tiger Lake support AVX-512/AMX and Rocket Lake supports AVX-512 as well but now their highest performance core in several years will not? WTF!

I just find it odd that they've invested so heavily in AVX-512 over the years, and now they seem to be backing away from it.

 

[Det0x]

Likely not, but it was still done haphazardly imo. Ice Lake and Tiger Lake support AVX-512/AMX and Rocket Lake supports AVX-512 as well but now their highest performance core in several years will not? WTF!

I just find it odd that they've invested so heavily in AVX-512 over the years, and now they seem to be backing away from it.

Kinda reminds me of the story with Nvidia and tessellation, when ATI finally court up, it wasn't important anymore..
So i take it Zen4 support AVX-512 ?

 

[Carfax83]

That would be my take as well. And if most enthusiasts disable the small cores permanently for whatever reason that’s going to call the strategy further into question.

I don't think anyone would disable them permanently. But some workloads do run notably faster with AVX-512, perhaps enough to outpace the impact of the 8 little cores.

 

[Carfax83]

So i take it Zen4 support AVX-512 ?

Probably, but likely by fusing two 256 bit instructions together like they did with Zen 1 and AVX2.

 

[jpiniero]

I don't think anyone would disable them permanently. But some workloads do run notably faster with AVX-512, perhaps enough to outpace the impact of the 8 little cores.

It'd be sort of annoying since it would be a BIOS setting. Are there any games which actually use AVX-512? The small cores might have some use.

Likely not, but it was still done haphazardly imo. Ice Lake and Tiger Lake support AVX-512/AMX

Neither of those support AMX. Only Sapphire. I don't think Alder supports it either.