Intel has used year tick-tock cadence. Which is, at first they shrink their previous design and then they do redesign which makes use of new processes's increased transistor density. For 10nm that shrink was CannonLake, redesigned uarch for 10nm was named as Sunny Cove. As what I think would be possible to backport to 14nm would be CannonLake, so they have AVX512 and few percent IPC improvement + Sunny Cove cache system, 48KB L1D + 512KB L2 which gives probably 5-10% of performance on top of Cannonlake.You're basically just saying that difference processes have different performance characteristics, which is true to an extent, but does not justify repipelining or any other dramatic change. Again, it's the same with a shrink. You don't redesign for the new process; you just pocket the gains as they come.
Besides, looking at Ice Lake, 10+ doesn't seem to have any performance advantage vs 14+++ to begin with.
But as there's some 5+ years between Skylake and Rocketlake there might be some other design changes too but SunnyCove which makes use of 10nm density with greatly increased OOO-structures and register files - I found it improbable that Intel could just reuse that design to 14nm. Or take it other way - if they could do that they haven't really exposed 10nm possibilities yet - even nowadays Intel should not be that far away with their designs.