Caches are the same. Same L1D of 48KB and L2 of 512KB. But cache size is just part of the picture. Like IntelUser2000 mentioned, backport process introduces additional challenges. For example L2 cache sizes might have grown in physical size and latency in clocks had to to be relaxed to meet those new constraints. Or 14nm thermals/clocking requirements forcing reduction of L2 ways from 8 to 4. Quite a few other ways to keep size the same and lower the perf -> TLB size and structure, sizes of OOP structures and queues.Isn't the 14nm Sunny Cove backport also somewhat reduced in cache sizes? Reducing the caches internal to the CPU would certainly reduce it's IPC as compared to a higher cache version on the smaller node that it was targeted at.
The key is where that "tax" is being paid, for example Intel already "paid" for 48KB L1D in relaxing latency from "4" cycles to 5. It seems scary penalty but in fact isn't so, cause 4 cycles was best case anyway. L2 latency nerf would hurt everything, while limits of TLB coverage would be more subtle.