uzzi38
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- Oct 16, 2019
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And I'm talking about that power draw for OG Skylake clocks. Best case scenario.I don't think they would bother if it was that bad. Remember I am talking about 200 W.
And I'm talking about that power draw for OG Skylake clocks. Best case scenario.I don't think they would bother if it was that bad. Remember I am talking about 200 W.
If it was that bad, why bother? Nothing would surprise me with Intel these days though.And I'm talking about that power draw for OG Skylake clocks. Best case scenario.
Well yeah, that's why I think it's a dumb idea that has no basis in reality.If it was that bad, why bother? Nothing would surprise me with Intel these days though.
Well, can it be heavily modified Sunny or willow Cove, maybe with smaller cache? Skylake-X cores on ring bus will provide no benefits on mainstream over existing 8 cores they have. Might as well be cometlake 8 coresWell yeah, that's why I think it's a dumb idea that has no basis in reality.
Rocket Lake may not be Skylake, but I can certainly tell you it's neither Sunny nor Willow Cove. Both would be extremely stupid moves.
I'm still sticking by the Skylake-X cores on a ring bus theory I had ages ago. It's the only thing that makes sense.
AVX512 and significantly larger caches.Well, can it be heavily modified Sunny or willow Cove, maybe with smaller cache? Skylake-X cores on ring bus will provide no benefits on mainstream over existing 8 cores they have. Might as well be cometlake 8 cores
If it's AVX-512 and based on Skylake, then its Skylake-X.The reason to use anything other than good ol regular Skylake would be to get better regular application/gaming performance, not AVX-512. It's definitely either Willow or Skylake.
On 14nm, it might end up more than 200mm2 even with GT1. The graphics part gets a real good shrink using the 10nm, closer to their 2.7x figure. If they want to alleviate the pressure on 14nm fabs, that wouldn't be the way to go.Yes they could theoretically use a different chip for the graphics part but this is unlikely for a GT1 with only 32 EUs. Overall this is clearly an indication of a Tigerlake version in 14nm.
I have doubts it'll reach 5GHz as its a new core while all 5GHz Intel chips have been refined little by little for many years now.Now I am in total agreement that if this thing is using Willow Cove that it will be drawing a ton of juice. But it should (better be?) able to still do 5 Ghz on all cores.
According to whom? Am I missing something?TGL-S is back on the table now
I mean it's a possibility. Not that it's definitely happening.According to whom? Am I missing something?
Yeah, if only it wasn't also on a roadmap that has been proven to be pretty accurate, I'd agree, the 10nm chiplet is a dumb sounding idea.Assuming the AVX512 and PCIe4 support is accurate, it pretty much rules out the possibility of Skylake. Plus there is Gen12 graphics. Yes they could theoretically use a different chip for the graphics part but this is unlikely for a GT1 with only 32 EUs. Overall this is clearly an indication of a Tigerlake version in 14nm.
I don't see it. Intel has . . . shall we say, highly morphological roadmaps as of late, but one of the things that's consistently on all their roadmaps is: no mention of TigerLake parts with more than 4c, and definitely not anything for their desktop sockets.I mean it's a possibility. Not that it's definitely happening.
Well there's a reason I said non-zero. I don't think it's likely, just a possibility. Would help if we knew properly which roadmaps were torched, but alas.I don't see it. Intel has . . . shall we say, highly morphological roadmaps as of late, but one of the things that's consistently on all their roadmaps is: no mention of TigerLake parts with more than 4c, and definitely not anything for their desktop sockets.
Intel is definitely going to be encouraging Water even with Comet. Remember that the base TDP is now 125 W.Also, to whoever said 5GHz might be possible with Rocket Lake, I'd like to say, how much do you enjoy running your CPU under LN2 all the time?
That's still Skylake.Intel is definitely going to be encouraging Water even with Comet. Remember that the base TDP is now 125 W.
Yes but SKL-X would be a downgrade for the mainstream, gaming IPC is much lower and only 8C, any additional work on this is a waste.If it's AVX-512 and based on Skylake, then its Skylake-X.
On 14nm, it might end up more than 200mm2 even with GT1. The graphics part gets a real good shrink using the 10nm, closer to their 2.7x figure. If they want to alleviate the pressure on 14nm fabs, that wouldn't be the way to go.
I could see a 14nm + 14nm part, aligning with earlier roadmaps. 14nm + 10nm seems too small unless they are planning on a refresh with the GPU getting a full 96EU version.
Probably something like the higher end Rocket U gets the 10 nm GPU chiplet, while the rest gets the 14 nm one. S would only get the 14 nm.In the tweakers roadmap there was only one RKL-U with 14+10nm, the other RKL-U and RKL-S was only 14nm.
How much of that is down to the core, and how much is down to the higher latency from mesh fabric? Put the same core with AVX-512 and extra cache on a ringbus, and I expect to see improved gaming performance.Yes but SKL-X would be a downgrade for the mainstream, gaming IPC is much lower and only 8C, any additional work on this is a waste.
Not on a ring-bus it wouldn't be.Yes but SKL-X would be a downgrade for the mainstream, gaming IPC is much lower and only 8C, any additional work on this is a waste.
How much of that is down to the core, and how much is down to the higher latency from mesh fabric? Put the same core with AVX-512 and extra cache on a ringbus, and I expect to see improved gaming performance.
Its a good way to get AVX-512 support across their whole lineup (finally), and would help encourage developers.
More stupid than spending millions of dollars porting Tigerlake back to 14nm, for a small market of enthusiasts?Intel told the highend Skylake is optimized for datacenter workloads. I don't think it's only a mesh issue, SKL-X only has 1 MB L3 whereas Skylake-S has 2 MB and with Willow Cove Intel goes up to 3MB per core. This is not a simple stepping change converting a SKL-X core onto a ringbus system, I would say this is a huge work if they really would do this, definitely not a trivial task. So much effort for a dead architecture which in the end won't be faster than CML, with 8 cores most likely slower. AVX 512 won't help them, they might gain a few percent in x265 benchmarks and that's it. To be honest this a a stupid idea to even think about.
Not to mention the fact that it'd barely be able to outperform the 'SKL-X on ringbus' idea too. Maybe an extra 5%, if you're incredibly, incredibly lucky.More stupid than spending millions of dollars porting Tigerlake back to 14nm, for a small market of enthusiasts?
There is something like 20 different instruction subsets under AVX512. Every Intel CPU lineup supports different subset group. Even IceLake doesn't support all of them (14 out of 20). https://en.wikipedia.org/wiki/AVX-512#CPUs_with_AVX-512Its a good way to get AVX-512 support across their whole lineup (finally), and would help encourage developers.