Discussion Intel current and future Lakes & Rapids thread

[mikk]

LPDDR4 isn't supposed to be in the initial CML-U chips?

The first wave of Comet Lake-U is just renamed, it's a stepping 12 of Whiskey Lake says Geekbench. No chance for LPDDR4.

 

[birdie]

In a related news:

Samsung’s 5nm EUV Technology Gets Closer: Tools by Cadence & Synopsys Certified

The new fabrication process enables chip designers to reuse 7LPP IP on ICs designed for 5LPE while enjoying all benefits the latter provides. When compared to 7LPP, the new technology has an up to 25% higher ‘logic efficiency’, it also enables chip developers to reduce power consumption of their designs by 20% or improve their performance by 10%.

At this point if I were an Intel CEO I would start producing Ice Lake CPUs using Samsung's foundries.

 

[JasonLD]

In a related news:

Samsung’s 5nm EUV Technology Gets Closer: Tools by Cadence & Synopsys Certified


At this point if I were an Intel CEO I would start producing Ice Lake CPUs using Samsung's foundries.

Samsung's 5nm is nowhere near TSMC 5nm or Intel's 7nm in terms of density. Samsung's "3nm" is competing against those nodes and it won't be ready until 2022.

 

[DrMrLordX]

Samsung's 5nm is nowhere near TSMC 5nm or Intel's 7nm in terms of density.

Can it compete with Intel 10nm in density? And, unlike Intel 10nm, can it function?

 

[extide]

And 7MB of L3 make very little sense as well. For example 6C dies have 6 partitions of 2MB of L3 cache. Can't really reduce that to 7MB?

I'm sure they could if they really wanted to, I mean heck there are existing 6C chips with 9MB L3. In fact the very laptop I am typing this on is an 8750H with 9MB L3.

That being said that slide looks fake, especially the X$ part, and 7MB L3 is just a totally weird number.

 

[JoeRambo]

I'm sure they could if they really wanted to, I mean heck there are existing 6C chips with 9MB L3. In fact the very laptop I am typing this on is an 8750H with 9MB L3.

9MB is 1536KB per L3 cache partition, perfectly fine and used by Intel many times in configurations like 6MB for 4C etc. 7MB is not really divisible.

But of course Intel can make it work if they want to, but in the time of AMD CPUs with 32/64MB L3 cache, such wicked configuration would be not wise?

 

[JasonLD]

Can it compete with Intel 10nm in density? And, unlike Intel 10nm, can it function?

It seems like Samsung's 5nm EUV is comparable to TSMC's 7nm+ in terms of density, so should be little more dense than Intel's 10nm. We haven't even got a first look at Samsung's 7nm which first product based on it isn't due until early next year so hard to say how it is going to perform.

 

[mikk]

Samsung's 5nm is nowhere near TSMC 5nm or Intel's 7nm in terms of density. Samsung's "3nm" is competing against those nodes and it won't be ready until 2022.

And by the way TSMC 7nm doesn't look impressive based on Zen2 , it only clocks to 4200-4300 Mhz typically with a pretty high Vcore demand.....only marginally better than 12nm. I mean Intels mobile Icelake ULV can go up to 4 Ghz, so possibly a theoretical 10nm desktop chip could match the speed of TSMC 7nm already. Also Navi looks quite big for 7nm (~251 mm], not sure if RDNA requires much more space or the density improvements from TSMC 7nm is smaller than expected somehow.

 

[IntelUser2000]

And by the way TSMC 7nm doesn't look impressive based on Zen2 , it only clocks to 4200-4300 Mhz typically with a pretty high Vcore demand.....only marginally better than 12nm.

This isn't TSMC sucking, but Intel having 4 years to work on 14nm. Broadwell clocked poorly, and it needed Skylake to do better. Also Intel historically had better performing transistors and they tuned their process to do the same.

What the 7nm and new processes are awesome at doing is with low power. Ryzen 3000 does really well on the power front for having 4GHz 12 cores. This is same with Intel 10nm. Icelake will be able to do it at lot lower power.

There's little point in comparing Intel nodes to Foundry nodes anyway. Intel aims to make their own products and they are quite different.

Skylake 4 core + iGPU has ~1.7 billion transistors? Bristol Ridge had 3 billion or so? Ryzen without iGPU has 4.9 billion?

If you add 4 cores to Skylake maybe you'll end up with 3 billion? Sure it seems a lot less dense, but then again 9900K performs on par with 8 core Ryzen chips so why does it matter?

 

[extide]

Yeah it's kinda funny that Intel having spent so much time optimizing 14nm will sort of make it harder to move to 10nm and 7nm as they have truly optimized the crap out of that 14nm process. It will take quite some time and tuning to get a future process to that level...

Even Skylake wasnt that great of a clocker, it wasnt until Kaby Lake that they really got the clocks up.

 

[Dayman1225]

Not entirely sure if this means anything at all... but I know that "Boot Camp" is an Apple Macbook thing.

https://twitter.com/i/web/status/1148234720930455552

ICL Macbook in the (near?) future?

 

[jpiniero]

Guessing more Rocket, which uses Icelake's platform.

 

[JasonLD]

Guessing more Rocket, which uses Icelake's platform.

Don't think there is Rocket suitable for Macbook or Macbook air on leaked roadmap.

 

[ikjadoon]

The first wave of Comet Lake-U is just renamed, it's a stepping 12 of Whiskey Lake says Geekbench. No chance for LPDDR4.

"Comet Lake = renamed Whiskey Lake" is a process limitation. I mean, isn't everything 14nm just renamed Skylake?

Whiskey Lake itself was just Kaby Lake-R, but it includes a handful of Spectre/Meltdown mitigations in hardware that apparently don't give away as much performance as the software mitigations.

Not that consumers really felt Spectre/Meltdown, anyways. The "meh" cooling of Whiskey Lake in dreadful 15 W chassis laptops probably had a larger effect.

 

[DrMrLordX]

It seems like Samsung's 5nm EUV is comparable to TSMC's 7nm+ in terms of density, so should be little more dense than Intel's 10nm. We haven't even got a first look at Samsung's 7nm which first product based on it isn't due until early next year so hard to say how it is going to perform.

Okay. Assuming Intel continues to flub 10nm through 2020 (which they might not), they won't have their own 7nm EUV process ready until 2021 where enterprise Xe will be used as a pipecleaner. To date, Xe is the only product that has been slated for Intel 7nm in 2021. That gives Intel a 2-year window to use (or license) Samsung nodes for desktop/consumer production (2020-2021). Come 2022, Intel needs to shift darn near every cutting-edge node product to their own 7nm EUV node or go up in flames.

 

[mikk]

"Comet Lake = renamed Whiskey Lake" is a process limitation. I mean, isn't everything 14nm just renamed Skylake?

Whiskey Lake itself was just Kaby Lake-R, but it includes a handful of Spectre/Meltdown mitigations in hardware that apparently don't give away as much performance as the software mitigations.

Not that consumers really felt Spectre/Meltdown, anyways. The "meh" cooling of Whiskey Lake in dreadful 15 W chassis laptops probably had a larger effect.

Whiskey Lake is on 14nm++ and KBL-R is on 14nm+, it's a refresh but not a renaming. The first stepping of Comet Lake-U is a pure renaming of WHL. The second stepping is coming also with 6 cores, so they can't simply rename it.

 

[epsilon84]

Yeah it's kinda funny that Intel having spent so much time optimizing 14nm will sort of make it harder to move to 10nm and 7nm as they have truly optimized the crap out of that 14nm process. It will take quite some time and tuning to get a future process to that level...

Even Skylake wasnt that great of a clocker, it wasnt until Kaby Lake that they really got the clocks up.

Ehh? 'Great' is all relative I guess. I had 2 6700Ks back in the day and they both hit 4.7GHz with relative ease. CFL has raised that bar by another 400MHz or so, but 4.7GHz is still nothing to sneeze at. I'd imagine AMD would absolutely dominate Intel right now if they could get 4.7GHz all core on their Ryzen 3000 chips, rather than 4.1 - 4.2GHz.

And to the poster who said that Intel kinda made things harder for themselves by optimising 14nm so much is spot on. It's almost made it impossible to surpass (at least from a clockspeed perspective).

So 10nm is supposed to be 18% higher IPC? But if it clocks 20% lower than 14nm+++++++++ you're actually getting performance regression. Guess Intel could follow AMDs 'more cores' approach. What other choice do they have?

 

[Dayman1225]

Intel announces new packaging stuffs at SemiCon West. Co-EMIB, ODI and MDIO

Article from the EETImes, WikiChip, ServeTheHome and Venture Beat

The chips they showed looked really cool and are based on 10nm.

Spoiler: Tweets and Images

https://twitter.com/i/web/status/1148629786576617472

https://twitter.com/i/web/status/1148630890399948800

 

[Markfw]

Intel announces new packaging stuffs at SemiCon West. Co-EMIB, ODI and MDIO

Article from the EETImes, WikiChip, ServeTheHome and Venture Beat

The chips they showed looked really cool and are based on 10nm.

Spoiler: Tweets and Images

https://twitter.com/i/web/status/1148629786576617472

https://twitter.com/i/web/status/1148630890399948800

It looks like what AMD has already done in Ryzen2/Rome.

 

[Abwx]

Skylake 4 core + iGPU has ~1.7 billion transistors? Bristol Ridge had 3 billion or so? Ryzen without iGPU has 4.9 billion?

About 3.4bn for SKL, Intel is undoubtly counting transistors functionality, wich mean that they count two transistors as being a single one since those two transistors are connected such that they act as a single one, FI rather than using two transistors to achieve an inverting gate they use four that will use the same power (at same frequency) but will switch typically 30% faster.

 

[jpiniero]

Don't think there is Rocket suitable for Macbook or Macbook air on leaked roadmap.

The comment underneath it makes it look like it doesn't have anything to do with Apple.

Although, looking at it further, it would be sort of weird if Apple did end up using Rocket Lake for the 13" MBP and use Comet Lake Y/H for the other models.

 

[IntelUser2000]

The chips they showed looked really cool and are based on 10nm.

Not all may be 10nm. They want to deliver two near full reticle sized Cascade Lake in a single package.

The package above with what seems like two very large dies plus 8 small ones could be Cooper Lake AP, using two Cascade Lake SP dies.

Cooper Lake AP with 56 cores + 8 stack HBM2 memory for 1TB/s bandwidth?

Rest might be 10nm FPGAs or even prototype chips.

It looks like what AMD has already done in Ryzen2/Rome.

It looks similar but its very different. Rome/Ryzen 2 can be used with non-silicon interposers and has been done for many years. Examples: Pentium D, Clarkdale, on-package PCH on Intel's U/Y chips, Intel's eDRAM chips.

Silicon interposers and EMIB type of technologies are used when you want really high bandwidth. This is why HBM2 for example needs such technologies. A single HBM2 chip in Kabylake G requires 256GB/s bandwidth.

 

[Dayman1225]

Not all may be 10nm. They want to deliver two near full reticle sized Cascade Lake in a single package.

I assume all 10nm since that is what David said. If some were 14nm I am sure he would have said so...

https://twitter.com/i/web/status/1148630890399948800

The package above with what seems like two very large dies plus 8 small ones could be Cooper Lake AP, using two Cascade Lake SP dies.

Cooper Lake AP with 56 cores + 8 stack HBM2 memory for 1TB/s bandwidth?

Could also be that rumored Icelake MCM CPU with HBM2

Or 2x Agilex with HBM2. Who knows... I am sure David's article coming on the weekend will have more details

 

[IntelUser2000]

I assume all 10nm since that is what David said. If some were 14nm I am sure he would have said so...

I'm assuming its dual Cascade Lake because the die size is quite large and the EETimes article talks about it. Based on the wide side of HBM2 being ~12mm2(11.87mm2) I'm getting more than 600mm2 as a size.

Early rumors of Icelake-AP with HBM2 had it using 2x22 core dies.

The Cascade Lake-AP line is bit of a disappointment now, but with HBM2 stacks enabling much increased memory bandwidth, and possibly using EMIB could allow it to carve a niche.

 

[beginner99]

The Cascade Lake-AP line is bit of a disappointment now, but with HBM2 stacks enabling much increased memory bandwidth, and possibly using EMIB could allow it to carve a niche.

Are niches good idea? i mean wasn't intels strategy to win by mostly being cheaper while not lacking too much in performance? Moving DEC and co farther and farther into niches. Is Intel getting "inteled" by AMD?