Intel announces Tri-gate "3-D" transistors for upcoming Ivy Bridge based processors

[Idontcare]

Strange the anouncement is after this anouncement
http://www.kurzweilai.net/ibm-shows-smallest-fastest-graphene-processor

That's awesome. I think their customers are still waiting for the HK/MG tech they announced back in 2007 for 45nm though.

 

[tommo123]

doesn't it generally go:

Intel shows tech - it will get used fairly soon (hkmg, tri-gate etc)
IBM shows tech - will get used, maybe within a decade?

 

[Idontcare]

LOL, true, and even then when it does get used it tends to turn out to be a dead-end. SiLK anyone? Gate-first HKMG?

What most folks don't realize is that IBM has a very fractured and disjointed R&D program.

The semi-practical stuff gets done at Fishkill, where the fab-club exists and operates.

The pie-in-the-sky R&D that tends to never see the light of a production fab is done by their Watson Research Center in Yorktown.

The guys in Fishkill, even the IBM'ers, are forever bitching and complaining about the literal impracticality of the design schemes and materials that are hatched in Yorktown. It is their reality.

This is why the 45nm HK/MG stuff never came to fruition, it was done as a one-off R&D demo by the Yorktown guys and had no basis in production-worthy integration.

Wattson is a lot like the Bell Labs of the 15 yrs ago, they do all kinds of cool R&D but they aren't really beholden to make it turn a profit, ever, so they tend to optimize things in the absence of cost considerations (including pesky trivial things like fab yield ).

It is the Fishkill teams that have to try and do something practical with the Wattson R&D, and a fair amount of it just gets scrapped and redone from the ground up because it is simply unmanufacturable (as was the case with SiLK).

 

[tommo123]

that sounds like a complete waste of $. unless the press they gather from the pie in the sky r+d gives enough PR to make it worthwhile? in this case, stealing a little from intels announcement

 

[Idontcare]

that sounds like a complete waste of $. unless the press they gather from the pie in the sky r+d gives enough PR to make it worthwhile? in this case, stealing a little from intels announcement

It delivers shareholder value by way of patent royalties and adding a premium to the stockprice based on perceived technological superiority.

Same reasons why Intel bothers to announce to the world that their xtors are HKMG or "3-D".

Marketing works, if it didn't then you wouldn't see this stuff being injected into the public domain.

 

[gog8rs]

that sounds like a complete waste of $. unless the press they gather from the pie in the sky r+d gives enough PR to make it worthwhile? in this case, stealing a little from intels announcement

IBM benefits a lot from the PR (and the patents). It's always funny when they produce something "wafer-scale" with e-beam lithography, though.

 

[CTho9305]

With 28nm mask-sets going for around $2.5m-$3m, and expected to go for ~$10m at 22-20nm, per-wafer production costs get rather spendy if you are making only 100 wfrs of a given product.

Wow, that's going to suck - it's going to be even harder to justify spinning a new revision or running an experiment.

I found the link I was referencing in the quoted post above.

It was an article in the most recent edition of Future Fab. It is free but you have to register with your email address.

(there is an e-beam litho article in there as well)

At any rate the article I was referring to starts on page 50.

http://www.future-fab.com/content/PDF/FF37_U_WP_MSS_Hui.pdf

Quite amazing to see 20% of their products are single-lot runs. 40% are single lot and double-lot runs.

Those guys would love to have the cost of migrating to a smaller node (even fewer wafers needed) for the higher performance but the mask-set costs are quite staggering on a per-wafer basis when you only need 25 wfrs.

How do chip revs and experiments get counted here?

I am no expert - I usually defer on this stuff to Idontcare - but it was my understanding that the original finFET designed used a thicker layer of oxide across the top as part of the self-aligned process and so it really was a dual gate even though the poly wrapped around on all three sides because the oxide etchstop on the top was too thick.

That's my understanding too. Intel figured out how to control oxides on 3 sides. Crazy!

 

[Idontcare]

Wow, that's going to suck - it's going to be even harder to justify spinning a new revision or running an experiment.

Yep, its the number one reason why old nodes remain in use at foundries.

The mask-set costs alone, regardless the shrink team costs, simply make it uneconomical to shrink low-volume products.

At TI we use to offer a catalog of roughly 19,000 different semiconductor IC's.

The sales volume of over half of those IC's were on the order of only needing 20 wafers per year production to satisfy demand.

Sure we could have shrunk the IC, taken it from 0.5um down to 130nm or 90nm, reducing the wafers needed from 20 to around 1 or 2. But the customers weren't going to pay an extra $10/chip to recover the costs associated with the shrink when spread out over so few product wafers.

I haven't updated this graph in a while, but it serves the purpose here in terms of lagging-edge node usage in a company that has a diversified product portfolio:

How do chip revs and experiments get counted here?

I don't know for certain but the article is intended to be a discussion regarding customer products which would lead me to believe they filtered out the background level of persistent one-off engineering experiments that are always underway as a matter of yield enhancement, process tweaks, CT reduction activities, etc.

 

[tweakboy]

Shouldn't we disable this in BIOS

Use the video card instead. tl

 

[exar333]

Shouldn't we disable this in BIOS

Use the video card instead. tl

What are you talking about?

 

[Idontcare]

What are you talking about?

Drunk posting, it ain't pretty.

 

[Phynaz]

Shouldn't we disable this in BIOS

Use the video card instead. tl

You either need to get on, or get off your meds.

 

[Phynaz]

Drunk posting, it ain't pretty.

At 8:30 in the morning? That's an early start!

 

[CTho9305]

Yep, its the number one reason why old nodes remain in use at foundries.

The mask-set costs alone, regardless the shrink team costs, simply make it uneconomical to shrink low-volume products.

At TI we use to offer a catalog of roughly 19,000 different semiconductor IC's.

The sales volume of over half of those IC's were on the order of only needing 20 wafers per year production to satisfy demand.

Sure we could have shrunk the IC, taken it from 0.5um down to 130nm or 90nm, reducing the wafers needed from 20 to around 1 or 2. But the customers weren't going to pay an extra $10/chip to recover the costs associated with the shrink when spread out over so few product wafers.

I was thinking more along the lines of revs on the same nodes for bugfixes, speed / yield improvement, etc. Even if masks are cheap, doing a shrink takes a lot of manpower.

I haven't updated this graph in a while, but it serves the purpose here in terms of lagging-edge node usage in a company that has a diversified product portfolio:

Cool graph. Was 0.15 a "pure optical" half-node, or why was the transition from 0.18 so dramatic?

 

[Dizon]

It delivers shareholder value by way of patent royalties and adding a premium to the stockprice based on perceived technological superiority.

Same reasons why Intel bothers to announce to the world that their xtors are HKMG or "3-D".

Marketing works, if it didn't then you wouldn't see this stuff being injected into the public domain.

Yeap, Idontcare is spot on. The day this news was announced, Intel stocks jumped by like 7%. Shares bought soared to 100M.

 

[PlasmaBomb]

Except for the fact that the gray line is pretty much purely theoretical - it could well be that it wouldn't have scaled as well in reality.

I'm pretty sure that Intel will have made test chips/wafers at 22nm (planar) to get that data from...

 

[PlasmaBomb]

Cool graph. Was 0.15 a "pure optical" half-node, or why was the transition from 0.18 so dramatic?

It certainly is a cool graph. Thank IDC.

Interesting to see how some nodes survive yet others rapidly disappear.

Seems like every other node does lasts longer- 500nm, 250nm, 150nm...

 

[Idontcare]

I was thinking more along the lines of revs on the same nodes for bugfixes, speed / yield improvement, etc. Even if masks are cheap, doing a shrink takes a lot of manpower.

Even if half of it was attributable to that, thus would mean 10% of TSMC's wafer volume comes from single-lot runs that are bug fixes and yield improvement steppings. That would be a LOT of WIP allocated for respin verification if you think about it.

Cool graph. Was 0.15 a "pure optical" half-node, or why was the transition from 0.18 so dramatic?

It certainly is a cool graph. Thank IDC.

Interesting to see how some nodes survive yet others rapidly disappear.

Seems like every other node does lasts longer- 500nm, 250nm, 150nm...

Since you guys seem to like the graph I went ahead and updated it with the most recent data:

The appearance of the anomalous node volume crashing to zero for every other node is just accounting on TSMC's behalf, they periodically intentionally roll the sales up into the next node.

For example in Q1 2000 they rolled the 1um revenue fraction into the 0.5um revenue number. They still sell 1um node products to this day, but they report the revenue for 1um products as if they were 0.5um products.

Same is true for 0.35um (rolled into 0.25um) and the 0.18um (rolled into 0.15um). The revenue volume did not actually go to zero, they just stopped breaking it out for reporting purposes.

Starting with 130nm they rolled up the revenue by node to include the half-node as well, and have done so ever since.

Oh, here's another cool little graph that shows the consistency of the ramp-rate in terms of revenue % as a function of business quarters since the node was released to production:

 

[PlasmaBomb]

Excellent update IDC :thumbsup:

 

[Phynaz]

Nice charts IDC.

 

[Bill Brasky]

I don't really have anything to contribute, but this thread has been a very satisfying read. Thanks for the info. :thumbsup:

 

[zebrax2]

From that graph .15um seems to be a pretty damn good investment

 

[drizek]

No, that has 0.18um in it as well after 2005.

 

[AtenRa]

What I meant to communicate was that you could take an existing planar xtor based on standard gate-oxide and transition to a 3D fin-based transistor, keeping the standard gate oxide but making it thicker than it was in the 2D case while retaining the same performance (Idrive).

Having the gate wrap around the active channel, as a fin-based xtor does, allows you to make the oxide thicker which lowers the leakage while retaining the same drive currents and switching speeds. In other words it is an alternative to HKMG, but it is not exclusive of it.

Doing both - HKMG and fin-based 3D xtor - is just even better. It is more Moore

It seems that Voltage Threshold (Vt) goes down because of the Fully Depleted design of the Tri-Gate transistor (no depletion region in the active channel) and that effects the Oxide Thickness (Tox) (High-K dielectric) because Vt and Tox are dependant and that effects the Sub Threshold leakage as well.

As you say, the thicker the Tox the less subthreshold leakage but we don’t want a very fat Tox (High-K) because we could have short channel effects. We could have Short channel effects with shorter channel lengths and in the Tri-Gate design the Channel length is dependant of the Gate thickness. As we shrink the Gate length the channel length will decrease and the higher the short channel effects.

I will have to say that I have no idea if all of that applies to the Tri-Gate ehehehe

Care to explain why the gate wrap around the active channel allows for a thicker Tox ??

 

[Lightflash]

Got to love reading this thread and being able to understand a small part of it due to certain members of the community sharing their expertise and previous work with us.

Thank you.