Intel announces Tri-gate "3-D" transistors for upcoming Ivy Bridge based processors

[Idontcare]

Care to explain why the gate wrap around the active channel allows for a thicker Tox ??

I'm gonna stumble around a bit here with my words as I'm trying to distill down into a few sentences the basics of something that encompasses thousands of pages of dissertations.

(ignoring the 3rd gate for the moment) By having the channel impacted by a gate on both the top and bottom (think 2D) you have dueling e-fields propagating from the gate into the channel.

In effect what you have is a channel that is half the thickness (depth) as a planar channel, requires half the time to "turn on", requires half the time to reach any given point on the Ion curve (basically switching speed is faster).

Lemme see if this half-assed diagram schematic communicates anything:

You see the red arrows in Step 1? The time it takes for those to "fully develop" is dependent on the gate oxide thickness (and the voltage).

Now look at the following:

Here I have intentionally made the fin thicker for illustration purposes, but you see how the channel is "red arrowed" all the quicker from all three sides because the gate wraps around the channel?

Because of this, if the gate-oxide were the same thickness for both the planar transistor and the finfet then the finfet xtor would reach fully "turn on" stage much much quicker (it would switch faster).

If you instead made the gate oxide thicker for the finfet, just enough such that the red arrows (from all sides) came to be in the same amount of time that the red arrows require for the planar xtor then you'd have a xtor that was the same speed but has less leakage because the gate-oxide was thicker.

(I'm intentionally cutting a lot of device physics corners here to simplify the discussion to get this point across)

edit: a couple good Intel papers to dive into for more -
Advanced Depleted-Substrate Transistors: Single-gate, Double-gate and Tri-gate

Tri-Gate Fully-Depleted CMOS Transistors: Fabrication, Design and Layout

 

[Phynaz]

Awesome IDC, thanks!

 

[drizek]

I'm gonna stumble around a bit here with my words as I'm trying to distill down into a few sentences the basics of something that encompasses thousands of pages of dissertations.

Always relevant. http://xkcd.com/895/

 

[Nemesis 1]

I'm gonna stumble around a bit here with my words as I'm trying to distill down into a few sentences the basics of something that encompasses thousands of pages of dissertations.

(ignoring the 3rd gate for the moment) By having the channel impacted by a gate on both the top and bottom (think 2D) you have dueling e-fields propagating from the gate into the channel.

In effect what you have is a channel that is half the thickness (depth) as a planar channel, requires half the time to "turn on", requires half the time to reach any given point on the Ion curve (basically switching speed is faster).

Lemme see if this half-assed diagram schematic communicates anything:

You see the red arrows in Step 1? The time it takes for those to "fully develop" is dependent on the gate oxide thickness (and the voltage).

Now look at the following:

Here I have intentionally made the fin thicker for illustration purposes, but you see how the channel is "red arrowed" all the quicker from all three sides because the gate wraps around the channel?

Because of this, if the gate-oxide were the same thickness for both the planar transistor and the finfet then the finfet xtor would reach fully "turn on" stage much much quicker (it would switch faster).

If you instead made the gate oxide thicker for the finfet, just enough such that the red arrows (from all sides) came to be in the same amount of time that the red arrows require for the planar xtor then you'd have a xtor that was the same speed but has less leakage because the gate-oxide was thicker.

(I'm intentionally cutting a lot of device physics corners here to simplify the discussion to get this point across)

edit: a couple good Intel papers to dive into for more -
Advanced Depleted-Substrate Transistors: Single-gate, Double-gate and Tri-gate

Tri-Gate Fully-Depleted CMOS Transistors: Fabrication, Design and Layout

IDC if I read this correctly . This 22nm transitor is trigate/ SOI ?

 

[Idontcare]

IDC if I read this correctly . This 22nm transitor is trigate/ SOI ?

You're not reading it right

In order to be SOI the silicon has to be on the insulator (oxide).

The oxide you see on either sides of the fin are just your standard moat oxide (aka "field oxide") used for the electrical isolation of the xtors themselves from their neighbors and has been used for decades.

There is a way to make finfets over SOI by starting with bulk-Si wafer though, you can see here:

http://www.electroiq.com/index/disp...nce__manufacturing_variability__and_cost.html

The problem with the above research comes in when you try to make fins of varying widths, as Intel does.

You can make Fin's starting with standard SOI wafers, I expect this is what IBM/Glofo are pursuing.

 

[Meghan54]

You're not reading it right

In order to be SOI the silicon has to be on the insulator (oxide).

The oxide you see on either sides of the fin are just your standard moat oxide (aka "field oxide") used for the electrical isolation of the xtors themselves from their neighbors and has been used for decades.

There is a way to make finfets over SOI by starting with bulk-Si wafer though, you can see here:

http://www.electroiq.com/index/disp...nce__manufacturing_variability__and_cost.html

The problem with the above research comes in when you try to make fins of varying widths, as Intel does.

You can make Fin's starting with standard SOI wafers, I expect this is what IBM/Glofo are pursuing.

First, thank you for all the time and effort you've put into "dumbing down" such complex subjects like you do....really helps us not so well versed in the subjects.

Second, do you think IBM/Glofo is close to what Intel is doing with theirs? I think I understand that Intel and IBM/Glofo are trying to solve a problem from two slightly differing roads, but seeing as how Intel is talking about this development going into Ivy Bridge, how close is IBM to actually putting their idea into a cpu, and will this help AMD out at all?

I understand my question(s) may be nonsense, given my lack of expertise in this area. But ask me about medicine and I can throw down with the best of them....one of my few areas of expertise.

 

[Arkadrel]

Everyone is always 2-3years behinde intel in fab tech.... give IMB and them guys 2years or so and they ll probably have their own version with FinFET as well.

 

[Idontcare]

First, thank you for all the time and effort you've put into "dumbing down" such complex subjects like you do....really helps us not so well versed in the subjects.

Second, do you think IBM/Glofo is close to what Intel is doing with theirs? I think I understand that Intel and IBM/Glofo are trying to solve a problem from two slightly differing roads, but seeing as how Intel is talking about this development going into Ivy Bridge, how close is IBM to actually putting their idea into a cpu, and will this help AMD out at all?

I understand my question(s) may be nonsense, given my lack of expertise in this area. But ask me about medicine and I can throw down with the best of them....one of my few areas of expertise.

IBM/GloFo won't go non-planar until 14nm, but HKMG on SOI gives them an advantage over HKMG on bulkSi so they may just not need it until then while still remaining competitive enough

 

[Abwx]

IBM/GloFo won't go non-planar until 14nm, but HKMG on SOI gives them an advantage over HKMG on bulkSi so they may just not need it until then while still remaining competitive enough

On this point, at least, we fully agree..

 

[Nemesis 1]

Reguardless of what the industry says . Intel was First with tri-gate . It would seem that many are not happy about this as they insist on using the term FinFet . Which is a 2 gated 3-d fin. So beings intel was First give them credit and stop dishing them by calling it Finfet . The links IDC gave cover this rather well they are not the same its ironic that many are saying it is .. Intel won the race . The prize is getting to name the process they developed.

 

[TuxDave]

Reguardless of what the industry says . Intel was First with tri-gate . It would seem that many are not happy about this as they insist on using the term FinFet . Which is a 2 gated 3-d fin. So beings intel was First give them credit and stop dishing them by calling it Finfet . The links IDC gave cover this rather well they are not the same its ironic that many are saying it is .. Intel won the race . The prize is getting to name the process they developed.

Intel was the first to have it ready for mass production. However, it is not the first to produce one.

Go Bears.

http://spectrum.ieee.org/semiconductors/design/the-origins-of-intels-new-transistor-and-its-future

(and yes I know that the 3D gate is different from a finfet, but I would rather call it a variation of the finfet instead of a whole new invention on its own)

 

[Nemesis 1]

Yes Dave I believe we have other links that say the same thing . Point is FINfet is a 2 gated transitor .3-d Tri-gate needs no explaning. As the term tri-gate says exactly what it is . Weres as finfet says little . Intels term will win out as its has a 2 year+ advantage. AMds best shot comes at 22 but AMD has other problems it will be dealing with at that node. I not sure but I believe it was said that 32nm(28) will be the one and only AMD with gate first. At 22nm(20) they go to gate last . So amd has to figure out gate last + Finfet 2gated transitors . Feel free to knock me around if I misunderstood this.

 

[Martimus]

Yes Dave I believe we have other links that say the same thing . Point is FINfet is a 2 gated transitor .3-d Tri-gate needs no explaning. As the term tri-gate says exactly what it is . Weres as finfet says little . Intels term will win out as its has a 2 year+ advantage. AMds best shot comes at 22 but AMD has other problems it will be dealing with at that node. I not sure but I believe it was said that 32nm(28) will be the one and only AMD with gate first. At 22nm(20) they go to gate last . So amd has to figure out gate last + Finfet 2gated transitors . Feel free to knock me around if I misunderstood this.

A FINFET usually refers to a 3D transistor, that has what looks like a "fin" on it. Thus a 3D Tri-gate transistor would be a "FINFET". The name is based on the fact that it is 3D and the "fin" shape to it, so the name does not specify how many gates are there.

 

[Nemesis 1]

Well lets look at daves link I believe thats were it was invented. I pretty sure they were talking 2 gates. If you go way back in this forum Me and other discussed TRIgate and finFet at that time They were NOT considered the same . The rest of the industry wants it to mean the same as intel owns a few patients for tri-gate as well as gate last . Just as IBM had patients on SOI pay to play is the game Intel got there first . IF everyone else is on 2 gated finfet and intel is alone at tri gate and intel process is better . Many companies may want intel as fab of choice . This is why the industry is tring to label 3-D tri-gate as a FINfet . After 10 years and billions in research dollars intel will not allow this . When you talk or review an intel product and its tri-gate and you label it as FINFET you will likely find yourself with nothing to review . Simply put read IDC links to intels trigate you will see clearly Intel says tri-gate and finfet are not the same .

I could pull some stuff off of the storge computer from 6 years ago and none said they were the same than , But now intel has a marketable products the rest of the industry is nervious and want to spread confussion. I just don't want to link to this PC as my daughters boy friend went to sites on this PC that infected it so I won't hook up to it . I should have my New SB up next week . So it should be cool than .

 

[AtenRa]

As far as i understand it, the original FinFET design was a quasi-planar Fully Depleted dual Gate so if we compare it to Intel's 3D Tri-Gate design yes they are not the same.

http://www.eecs.berkeley.edu/~jbokor/Full_text_pubs/99-137.pdf

 

[Martimus]

You know what, I have JFET, and MOSFETS, and P-type and N-type versions of each, yet all of them are Transistors. Just because all FINFETS aren't the same, doesn't mean they aren't FINFETS.

You do realize the name FINFET just means it is a 3D transistor, right? It doesn't specify anything else about the transistor.

The distinguishing characteristic of the FinFET is that the conducting channel is wrapped by a thin silicon "fin", which forms the gate of the device. The thickness of the fin (measured in the direction from source to drain) determines the effective channel length of the device.

http://en.wikipedia.org/wiki/Finfet

 

[Idontcare]

As far as i understand it, the original FinFET design was a quasi-planar Fully Depleted dual Gate so if we compare it to Intel's 3D Tri-Gate design yes they are not the same.

http://www.eecs.berkeley.edu/~jbokor/Full_text_pubs/99-137.pdf

Don't get hung up on the appearance of a semantic difference in the vernacular.

Intel's 3D tri-gate xtor is a FINFet, specifically it is a triple-gate finfet but you can have dual-gate and single-gate finfets as well.

In other words the distinction to be made regarding Intel's 3D transistors is not that they are Finfets or some other fet derivative but that they are triple-gate finfets. The triple-gate implementation is the distinguishing feature.

But finfets they are, to be sure. Just as I am an American, but more specifically I am a male American. To my wife the distinguishing attribute is the fact that I am male, not so much that I am an American. But one is not exclusive of the other, nor is one inclusive of the other. But to describe me it would be appropriate to employ both terms.

To simply refer to Intel's 22nm xtors as "3D triple-gate" is not enough, you are failing to provide a detailed enough description as to convey the geometrical arrangement of the 3D structure itself.

Likewise to refer to them simply as "finfets" is also not enough information.

To say it is a tri-gate Finfet tells me all I need to know in order to know exactly what Intel implemented.

However, at this point it is sufficient to simply refer to them as "Intel's finfet" and we all pretty much understand that you aim to discuss their tri-gate transistor since they have spent a lot of money to advertise and associate themselves with their 22nm xtors at this point.

We all know its a tri-gate finfet transistor. Intel did not coin the term FinFet though and in keeping with tradition they have pursued their own brand naming efforts on the matter.

Remember your history of 64bit x86? AMD did it first and called it AMD64...Intel wasn't about to advertise that they had AMD64 in their P4 CPU's though so they rebranded it as "EM64T".

Try not to get to wrapped up in the branding efforts that are going in here. These are tri-gate finfets, pretty darn nice ones at that given the use of HKMG as well.

 

[AtenRa]

I was comparing the original FinFET design vs the Intel's 3D Tri-Gate and you have to agree that the first is a planar dual gate when the later has a vertical Fin (3D) (Yes it is a FinFET) and 3 gates so the designs are not the same.

I will agree that both designs are FinFET's and there are more designs with Gate all around (4 Gates) etc.

Question,

I will like to thank you first for the nice presentation for the E-field in the channel of the 3 Gate transistor,

From the bellow diagram it is clear that the 22nm 3D Tri-Gate advantage is more down to lower Voltage than at Higher V where High End CPUs will be operate.

The question is, does that has anything to do with a Thicker Tox vs the Planar 22nm ?? or is it a FinFET design characteristic ??

What i mean is, did Intel intentionally made the Tox thicker in order to have lower leakage and lower Gate delay (higher performance) at lower Voltages where Mobile and SOC's chips will benefit most ?? and at the same time they managed to keep the same Gate delay as the Planar 22nm at 1V (actually is a little better than the planar).

Im asking to see if they have starting to focus more at the mobile/SOCs and keep a nice ~20% higher performance for the High End CPUs (from the manufacturing point of view) per every shrinking process.

 

[Idontcare]

I was comparing the original FinFET design vs the Intel's 3D Tri-Gate and you have to agree that the first is a planar dual gate when the later has a vertical Fin (3D) (Yes it is a FinFET) and 3 gates so the designs are not the same.

I will agree that both designs are FinFET's and there are more designs with Gate all around (4 Gates) etc.

Question,

I will like to thank you first for the nice presentation for the E-field in the channel of the 3 Gate transistor,

From the bellow diagram it is clear that the 22nm 3D Tri-Gate advantage is more down to lower Voltage than at Higher V where High End CPUs will be operate.

The question is, does that has anything to do with a Thicker Tox vs the Planar 22nm ?? or is it a FinFET design characteristic ??

What i mean is, did Intel intentionally made the Tox thicker in order to have lower leakage and lower Gate delay (higher performance) at lower Voltages where Mobile and SOC's chips will benefit most ?? and at the same time they managed to keep the same Gate delay as the Planar 22nm at 1V (actually is a little better than the planar).

Im asking to see if they have starting to focus more at the mobile/SOCs and keep a nice ~20% higher performance for the High End CPUs (from the manufacturing point of view) per every shrinking process.

Heh, all excellent questions to which I really don't know the answers.

What little I know I am happy to share but I am also quite aware of how little I know and your questions are very much outside the small little island of knowledge I possess on the subject at this time.

If I ever come across some good papers on the subject, or get a chance to have a download over dinner with a fellow engineer, I'll happily share what I have learned when/if that time comes.

I can make educated guesses as to the likely answers based on the boundary conditions that device physics in general places on these devices, but to answer your questions we really need an Intel engineer to chime in at this point and spill some beans on the specifics.

 

[Phynaz]

I can make educated guesses as to the likely answers

Please do!

Speculate away!

 

[TuxDave]

I was comparing the original FinFET design vs the Intel's 3D Tri-Gate and you have to agree that the first is a planar dual gate when the later has a vertical Fin (3D) (Yes it is a FinFET) and 3 gates so the designs are not the same.

I'm assuming you're referring to the paper you linked:
http://www.eecs.berkeley.edu/~jbokor/Full_text_pubs/99-137.pdf

How is that a planar dual gate? It clearly has a vertical fin as noted in the 2nd sentence of the introduction.