Intel announces Tri-gate "3-D" transistors for upcoming Ivy Bridge based processors

[Phynaz]

You'll get no argument from me regarding the superiority of the cost-benefits results, which is all that I think Phynaz was driving at.

Actually in this case I was actually talking about chip performance.

There is a contingent of people that claim AMD chips are superior because they are manufactured using wet litho. Such as the post from Jimbo that says now it will we can compare who gets better performance because now both companies are using wet litho.

The point I make is wet litho is expensive and complex. You don't use it because you want to, you use it because you have to.

Ignoring design rules, given the same design, the chip will perform the same regardless of the lithography process used.

 

[drizek]

Does anyone really argue that Phenom II is better than Nehalem?

 

[Majic 7]

Does anyone really argue that Phenom II is better than Nehalem?

I've seen claims that it is smoother.

 

[tincart]

Does anyone really argue that Phenom II is better than Nehalem?

My Phenom II is better than Nehalem in the sense that I own the Phenom II, but not the Nehalemn. If I owned a Nehalem chip as well, I would have to reconsider my position.

 

[Phynaz]

Does anyone really argue that Phenom II is better than Nehalem?

Plenty. Some people claim the benchmarks are biased and people publishing the benchmarks are paid off by Intel.

 

[drizek]

Well the intel platform is unattractive for a lot of reasons. I did buy a phenom II myself. But comparing just the chips, intel is clearly ahead.

 

[WhoBeDaPlaya]

I was really surprised at TSMC's volume versus lot-count for mask usage. It was made public recently, let me see if I can find that link. It really supported the argument that unless you have extremely high-volume parts on these leading edge nodes the cost of the maskset (which is higher for dry vs litho because of more masks being needed for double-patterning) then ebeam write without masks was the superior cost-benefit approach.

Really? I used an old Raith 150 clunker a lot for my doctoral research and can't see how that would be more cost effective than a mask set.

 

[Martimus]

Plenty. Some people claim the benchmarks are biased and people publishing the benchmarks are paid off by Intel.

Who has said this, and when did they say it? I sincerely doubt it is the epidemic of misinformation that you are making it out to be.

If anything I have seen maybe one or two people who make allegations of conspiracy on both sides of the fence, which is far and away the minority of posters here. Since the ignore function came about on this board, I think many don't even see most of these crazy conspiracy posts anymore.

 

[Phynaz]

Who has said this, and when did they say it? I sincerely doubt it is the epidemic of misinformation that you are making it out to be.

Which part of my post are you asking about?

There are plenty of people that think a PhenomII is superior to Nahalem, or some people that claim review sites cheat on benchmarks to make Intel look good?

 

[blastingcap]

All I can say is that I'm glad I did not get a Sandy Bridge, especially with the mobo problems. Ivy Bridge here I come.

 

[techforums]

I figure amdzone is one of them

 

[Idontcare]

Really? I used an old Raith 150 clunker a lot for my doctoral research and can't see how that would be more cost effective than a mask set.

With 28nm mask-sets going for around $2.5m-$3m, and expected to go for ~$10m at 22-20nm, per-wafer production costs get rather spendy if you are making only 100 wfrs of a given product. If you are making 50,000 wfrs a month then the mask-set cost is rapidly diluted across hundreds of thousands of wafers.

I spent 3yrs on a team (not full-time of course) that was dedicated to making a high-performance capacitor (MIMCAP) component whose total integration was confined to a single-mask adder for the overall integration flow.

Had the production cost budget allowed for a 2-mask adder capacitor design we could have been in a matter of weeks, the 1-mask adder constraint (purely driven by production cost priorities) turned it into a 3+ yr project.

 

[AtenRa]

Yeah that is pretty much how these cost-driven decisions are broken down. Do you take the cost up-front and then break it down over many more wafers so you make out ahead in the end, or do you take a lower-cost development path but one in which your per-wafer production costs are higher (but because of your lower-ish volumes, you actually make out ahead in the end that way too).

The SOI vs bulk-Si always made perfect economic sense to me with respect to the companies that use SOI and those who do not. I suspect the situation is similar for FD-SOI.

Why have higher per-wafer production costs if you have large enough production volume to justify investing more on R&D, getting comparable performance, but having slightly lower production costs?

Because of the disparate production volumes between Intel and AMD (GloFo) it makes sense that they manage the economics of R&D versus production costs as they do IMO.

One more reason they didn’t use SOI but researched heavily on HKMG could be the 3D tri-Gate Transistors, what I mean

The High-K dielectric was made in order to minimize the leakage from between the Gate and the Source-Drain because the space between the Gate and the Si was getting thinner and thinner and SiO2 oxide could not be used any more as an insulator. They also replaced the Gate material with a Metal and so we have the High-K Metal Gate (HKMG) process.

In a planar transistor (2D) the High-K dielectric only occupies a small region between the Gate and the Si substrate but in Tri-Gate transistor the Gate wraps around the source and the drain in three dimensions and so we have more area for the High-K dielectric to insulate the gate from the Source and the drain.
But because we shrink to 22nm the thickness of the insulator (High-K) becomes smaller (Thinner) and you have to invest in R&D not only for the thinner part but for the larger area you have to insulate.

So perhaps HKMG was the ticket for the tri-Gate transistors at the end ??

 

[Idontcare]

I was really surprised at TSMC's volume versus lot-count for mask usage. It was made public recently, let me see if I can find that link. It really supported the argument that unless you have extremely high-volume parts on these leading edge nodes the cost of the maskset (which is higher for dry vs litho because of more masks being needed for double-patterning) then ebeam write without masks was the superior cost-benefit approach.

I found the link I was referencing in the quoted post above.

It was an article in the most recent edition of Future Fab. It is free but you have to register with your email address.

(there is an e-beam litho article in there as well)

At any rate the article I was referring to starts on page 50.

http://www.future-fab.com/content/PDF/FF37_U_WP_MSS_Hui.pdf

Quite amazing to see 20% of their products are single-lot runs. 40% are single lot and double-lot runs.

Those guys would love to have the cost of migrating to a smaller node (even fewer wafers needed) for the higher performance but the mask-set costs are quite staggering on a per-wafer basis when you only need 25 wfrs.

 

[Phynaz]

One more reason they didn’t use SOI but researched heavily on HKMG could be the 3D tri-Gate Transistors, what I mean

<Snip>

So perhaps HKMG was the ticket for the tri-Gate transistors at the end ??

Funny, that was also what I was thinking.

 

[Idontcare]

In a planar transistor (2D) the High-K dielectric only occupies a small region between the Gate and the Si substrate but in Tri-Gate transistor the Gate wraps around the source and the drain in three dimensions and so we have more area for the High-K dielectric to insulate the gate from the Source and the drain.
But because we shrink to 22nm the thickness of the insulator (High-K) becomes smaller (Thinner) and you have to invest in R&D not only for the thinner part but for the larger area you have to insulate.

So perhaps HKMG was the ticket for the tri-Gate transistors at the end ??

I see exactly where you are headed with this line of thinking but the reality is the opposite actually. Going multi-gate, the fact you have more "gate area to channel volume ratio" means you can back off on the gate thinness (make it thicker) and reduce leakage while keeping the same Ioff and same leakage at Ion.

3D was one avenue that actually stood a chance at delaying the transition to HKMG, not the other way around.

Doing HKMG on a FIN-based 3D xtor is like having your cake and eating it too. Its all gravy, pure sugar.

From a scalability standpoint they've set themselves up to scale down to the 5-7nm node here before needing to abandon a silicon-based channel. They may still abandon it for a III-V based channel circa 10nm, but they need not do that at this point given the HKMG component is there already.

I'm still astounded that Intel did this for 22nm. HKMG at 45nm was impressive, this is just astounding.

 

[RobertPters77]

Does anyone really argue that Phenom II is better than Nehalem?

abwx.

 

[Ajay]

I see exactly where you are headed with this line of thinking but the reality is the opposite actually. Going multi-gate, the fact you have more "gate area to channel volume ratio" means you can back off on the gate thinness (make it thicker) and reduce leakage while keeping the same Ioff and same leakage at Ion.

So which is it, does < gate area/channel volume mean you can/must go thinner, or you can/must go thicker - that sentence seems ambiguous. TIA!


So, what ever the case is, it looks like Intel is going to kick AMD's arse even more starting sometime in 2012. Do you know anything about AMD's process evolution going forward?

 

[HopJokey]

So which is it, does < gate area/channel volume mean you can/must go thinner, or you can/must go thicker - that sentence seems ambiguous. TIA!


So, what ever the case is, it looks like Intel is going to kick AMD's arse even more starting sometime in 2012. Do you know anything about AMD's process evolution going forward?

AMD sold all their fabs technically to GloFlo and now relies on foundry's such as GloFlo, TSMC, etc. for the manufacturing of their chip designs.

 

[Idontcare]

So which is it, does < gate area/channel volume mean you can/must go thinner, or you can/must go thicker - that sentence seems ambiguous. TIA!


So, what ever the case is, it looks like Intel is going to kick AMD's arse even more starting sometime in 2012. Do you know anything about AMD's process evolution going forward?

What I meant to communicate was that you could take an existing planar xtor based on standard gate-oxide and transition to a 3D fin-based transistor, keeping the standard gate oxide but making it thicker than it was in the 2D case while retaining the same performance (Idrive).

Having the gate wrap around the active channel, as a fin-based xtor does, allows you to make the oxide thicker which lowers the leakage while retaining the same drive currents and switching speeds. In other words it is an alternative to HKMG, but it is not exclusive of it.

Doing both - HKMG and fin-based 3D xtor - is just even better. It is more Moore

Regarding AMD and 2012...it remains to be seen just how necessary the 22nm 3D tri-gate xtor tech is. The HKMG stuff was nice for 45nm but as we've seen from AMD it is/was not entirely necessary. The same could be said of immersion-litho and 45nm...AMD did it but Intel showed us it wasn't entirely necessary.

So come 2012, this may be sexy cool stuff for us enthusiasts to talk about but it may not really translate into silly sexy tangible gains at the product level.

Think about all the hoopla Intel put into publicizing their transition from domino to static CMOS with Nehalem. Sure Nehalem was awesome, and performance/watt improved all right, but it wasn't like it doubled or something magically delicious like that.

Simple power-gating did more for power-management than HKMG and static CMOS combined (look at 40nm Bobcat that has no SOI, no HKMG, no benefits of static CMOS, etc).

 

[Ajay]

What I meant to communicate was that you could take an existing planar xtor based on standard gate-oxide and transition to a 3D fin-based transistor, keeping the standard gate oxide but making it thicker than it was in the 2D case while retaining the same performance (Idrive).

Having the gate wrap around the active channel, as a fin-based xtor does, allows you to make the oxide thicker which lowers the leakage while retaining the same drive currents and switching speeds. In other words it is an alternative to HKMG, but it is not exclusive of it.

Doing both - HKMG and fin-based 3D xtor - is just even better. It is more Moore

Regarding AMD and 2012...it remains to be seen just how necessary the 22nm 3D tri-gate xtor tech is. The HKMG stuff was nice for 45nm but as we've seen from AMD it is/was not entirely necessary. The same could be said of immersion-litho and 45nm...AMD did it but Intel showed us it wasn't entirely necessary.

So come 2012, this may be sexy cool stuff for us enthusiasts to talk about but it may not really translate into silly sexy tangible gains at the product level.

Think about all the hoopla Intel put into publicizing their transition from domino to static CMOS with Nehalem. Sure Nehalem was awesome, and performance/watt improved all right, but it wasn't like it doubled or something magically delicious like that.

Simple power-gating did more for power-management than HKMG and static CMOS combined (look at 40nm Bobcat that has no SOI, no HKMG, no benefits of static CMOS, etc).

Thanks, this explanation sheds allot of light on the issue. So right now 3D tri-gate may be more about marketing than substantial product gains - but for the future it's much more important. And, AMD may be able to compete with less sophisticated technologies. Interesting.

 

[Ajay]

AMD sold all their fabs technically to GloFlo and now relies on foundry's such as GloFlo, TSMC, etc. for the manufacturing of their chip designs.

Yes, but I think AMD still pretty much drives GloFlo's process improvements - at least in terms of targets that need to be hit to support up coming designs.

 

[drizek]

Simple power-gating did more for power-management than HKMG and static CMOS combined (look at 40nm Bobcat that has no SOI, no HKMG, no benefits of static CMOS, etc).

Yes, and cortex A8 on bulk 65nm is more well suited for mobile devices than atom on whatever fancy process intel comes up with. Is even 22nm going to be able to put x86 into a Palm Pre or iPhone 3G form factor? And the pre overclocks to up to 1.2GHz.

 

[LiuKangBakinPie]

Everything is going 3d this days. Even Intel jumped on the bandwagon

 

[LiuKangBakinPie]

http://www.bbc.co.uk/news/technology-13283882




Anand's take on this announcement. http://www.anandtech.com/show/4313/...nm-3d-trigate-transistors-shipping-in-2h-2011

Strange the anouncement is after this anouncement
http://www.kurzweilai.net/ibm-shows-smallest-fastest-graphene-processor